Search

David A. Foster

Examiner (ID: 9207)

Most Active Art Unit
2835
Art Unit(s)
2841, 2835, 2103
Total Applications
393
Issued Applications
365
Pending Applications
18
Abandoned Applications
9

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6490004 [patent_doc_number] => 20100009531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'METHODS OF FORMING A CONTACT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/499832 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20100009531.pdf [firstpage_image] =>[orig_patent_app_number] => 12499832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499832
Methods of forming a contact structure Jul 8, 2009 Issued
Array ( [id] => 7965875 [patent_doc_number] => 07939421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Method for fabricating integrated circuit structures' [patent_app_type] => utility [patent_app_number] => 12/499622 [patent_app_country] => US [patent_app_date] => 2009-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3382 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/939/07939421.pdf [firstpage_image] =>[orig_patent_app_number] => 12499622 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499622
Method for fabricating integrated circuit structures Jul 7, 2009 Issued
Array ( [id] => 6220974 [patent_doc_number] => 20100055882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'Junction Termination Extension with Controllable Doping Profile and Controllable Width for High-Voltage Electronic Devices' [patent_app_type] => utility [patent_app_number] => 12/497721 [patent_app_country] => US [patent_app_date] => 2009-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7374 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20100055882.pdf [firstpage_image] =>[orig_patent_app_number] => 12497721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497721
Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices Jul 5, 2009 Issued
Array ( [id] => 6375159 [patent_doc_number] => 20100081248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/495731 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2290 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20100081248.pdf [firstpage_image] =>[orig_patent_app_number] => 12495731 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495731
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Jun 29, 2009 Abandoned
Array ( [id] => 6293111 [patent_doc_number] => 20100159663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'METHOD OF FABRICATING HIGH INTEGRATED SEMICONDUCTOR APPARATUS, AND SEMICONDUCTOR APPARATUS FABRICATED THEREBY' [patent_app_type] => utility [patent_app_number] => 12/495711 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3073 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20100159663.pdf [firstpage_image] =>[orig_patent_app_number] => 12495711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495711
Method of fabricating high integrated semiconductor apparatus, and semiconductor apparatus fabricated thereby Jun 29, 2009 Issued
Array ( [id] => 6327387 [patent_doc_number] => 20100327280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'SCALING OF BIPOLAR TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/493383 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7948 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327280.pdf [firstpage_image] =>[orig_patent_app_number] => 12493383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493383
Scaling of bipolar transistors Jun 28, 2009 Issued
Array ( [id] => 5461556 [patent_doc_number] => 20090321756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'LED Package Structure and Method of Packaging the Same' [patent_app_type] => utility [patent_app_number] => 12/492606 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12571 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321756.pdf [firstpage_image] =>[orig_patent_app_number] => 12492606 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492606
LED package structure and method of packaging the same Jun 25, 2009 Issued
Array ( [id] => 5495915 [patent_doc_number] => 20090263943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/492276 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6943 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20090263943.pdf [firstpage_image] =>[orig_patent_app_number] => 12492276 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492276
Method of fabricating semiconductor integrated circuit device Jun 25, 2009 Issued
Array ( [id] => 4624772 [patent_doc_number] => 08004073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Integrated circuit packaging system with interposer and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/486568 [patent_app_country] => US [patent_app_date] => 2009-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3757 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004073.pdf [firstpage_image] =>[orig_patent_app_number] => 12486568 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/486568
Integrated circuit packaging system with interposer and method of manufacture thereof Jun 16, 2009 Issued
Array ( [id] => 5394953 [patent_doc_number] => 20090315016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'ATOMIC LAYER DEPOSITION FOR FUNCTIONALIZING COLLOIDAL AND SEMICONDUCTOR PARTICLES' [patent_app_type] => utility [patent_app_number] => 12/485784 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315016.pdf [firstpage_image] =>[orig_patent_app_number] => 12485784 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/485784
Atomic layer deposition for functionalizing colloidal and semiconductor particles Jun 15, 2009 Issued
Array ( [id] => 5569857 [patent_doc_number] => 20090253235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/484618 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12108 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20090253235.pdf [firstpage_image] =>[orig_patent_app_number] => 12484618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484618
Method of manufacturing semiconductor device with offset sidewall structure Jun 14, 2009 Issued
Array ( [id] => 54067 [patent_doc_number] => 07772643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Methods of fabricating semiconductor device having a metal gate pattern' [patent_app_type] => utility [patent_app_number] => 12/457323 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772643.pdf [firstpage_image] =>[orig_patent_app_number] => 12457323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457323
Methods of fabricating semiconductor device having a metal gate pattern Jun 7, 2009 Issued
Array ( [id] => 7518777 [patent_doc_number] => 07972878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Quantum dot memory' [patent_app_type] => utility [patent_app_number] => 12/478084 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8692 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/972/07972878.pdf [firstpage_image] =>[orig_patent_app_number] => 12478084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/478084
Quantum dot memory Jun 3, 2009 Issued
Array ( [id] => 5533628 [patent_doc_number] => 20090233416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'FLASH MEMORY DEVICES COMPRISING PILLAR PATTERNS AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/471521 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6718 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20090233416.pdf [firstpage_image] =>[orig_patent_app_number] => 12471521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/471521
FLASH MEMORY DEVICES COMPRISING PILLAR PATTERNS AND METHODS OF FABRICATING THE SAME May 25, 2009 Abandoned
Array ( [id] => 5533645 [patent_doc_number] => 20090233433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Semiconductor device having silicon layer in a gate electrode' [patent_app_type] => utility [patent_app_number] => 12/453737 [patent_app_country] => US [patent_app_date] => 2009-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5847 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20090233433.pdf [firstpage_image] =>[orig_patent_app_number] => 12453737 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453737
Semiconductor device having silicon layer in a gate electrode May 19, 2009 Issued
Array ( [id] => 4595734 [patent_doc_number] => 07981711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Manufacture method of a multilayer structure having non-polar a-plane {11-20} III-nitride layer' [patent_app_type] => utility [patent_app_number] => 12/468138 [patent_app_country] => US [patent_app_date] => 2009-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3780 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/981/07981711.pdf [firstpage_image] =>[orig_patent_app_number] => 12468138 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/468138
Manufacture method of a multilayer structure having non-polar a-plane {11-20} III-nitride layer May 18, 2009 Issued
Array ( [id] => 6260510 [patent_doc_number] => 20100296691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'ELECTROMECHANICAL VIBRATION CONVERTER FOR TACTILE ACOUSTIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/468240 [patent_app_country] => US [patent_app_date] => 2009-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8332 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20100296691.pdf [firstpage_image] =>[orig_patent_app_number] => 12468240 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/468240
ELECTROMECHANICAL VIBRATION CONVERTER FOR TACTILE ACOUSTIC APPARATUS May 18, 2009 Abandoned
Array ( [id] => 5551454 [patent_doc_number] => 20090285440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Electroacoustic tranducing device' [patent_app_type] => utility [patent_app_number] => 12/453497 [patent_app_country] => US [patent_app_date] => 2009-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2646 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20090285440.pdf [firstpage_image] =>[orig_patent_app_number] => 12453497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453497
Electroacoustic tranducing device May 12, 2009 Abandoned
Array ( [id] => 5551453 [patent_doc_number] => 20090285439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Electroacoustic transducing device' [patent_app_type] => utility [patent_app_number] => 12/453496 [patent_app_country] => US [patent_app_date] => 2009-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8918 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20090285439.pdf [firstpage_image] =>[orig_patent_app_number] => 12453496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453496
Electroacoustic transducing device May 12, 2009 Issued
Array ( [id] => 4612826 [patent_doc_number] => 07989257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Polysilazane, method of synthesizing polysilazane, composition for manufacturing semiconductor device, and method of manufacturing semiconductor device using the composition' [patent_app_type] => utility [patent_app_number] => 12/415309 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989257.pdf [firstpage_image] =>[orig_patent_app_number] => 12415309 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/415309
Polysilazane, method of synthesizing polysilazane, composition for manufacturing semiconductor device, and method of manufacturing semiconductor device using the composition Mar 30, 2009 Issued
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