
David A. Foster
Examiner (ID: 9207)
| Most Active Art Unit | 2835 |
| Art Unit(s) | 2841, 2835, 2103 |
| Total Applications | 393 |
| Issued Applications | 365 |
| Pending Applications | 18 |
| Abandoned Applications | 9 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6490004
[patent_doc_number] => 20100009531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-14
[patent_title] => 'METHODS OF FORMING A CONTACT STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/499832
[patent_app_country] => US
[patent_app_date] => 2009-07-09
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[pdf_file] => publications/A1/0009/20100009531.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/499832 | Methods of forming a contact structure | Jul 8, 2009 | Issued |
Array
(
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[patent_doc_number] => 07939421
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[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Method for fabricating integrated circuit structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/499622 | Method for fabricating integrated circuit structures | Jul 7, 2009 | Issued |
Array
(
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[patent_doc_number] => 20100055882
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[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'Junction Termination Extension with Controllable Doping Profile and Controllable Width for High-Voltage Electronic Devices'
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[patent_app_number] => 12/497721
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/497721 | Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices | Jul 5, 2009 | Issued |
Array
(
[id] => 6375159
[patent_doc_number] => 20100081248
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[patent_issue_date] => 2010-04-01
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
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[patent_app_number] => 12/495731
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Array
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[patent_title] => 'METHOD OF FABRICATING HIGH INTEGRATED SEMICONDUCTOR APPARATUS, AND SEMICONDUCTOR APPARATUS FABRICATED THEREBY'
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Array
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Array
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[patent_title] => 'LED Package Structure and Method of Packaging the Same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/492606 | LED package structure and method of packaging the same | Jun 25, 2009 | Issued |
Array
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[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
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Array
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[patent_title] => 'Integrated circuit packaging system with interposer and method of manufacture thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/486568 | Integrated circuit packaging system with interposer and method of manufacture thereof | Jun 16, 2009 | Issued |
Array
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[patent_issue_date] => 2009-12-24
[patent_title] => 'ATOMIC LAYER DEPOSITION FOR FUNCTIONALIZING COLLOIDAL AND SEMICONDUCTOR PARTICLES'
[patent_app_type] => utility
[patent_app_number] => 12/485784
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/485784 | Atomic layer deposition for functionalizing colloidal and semiconductor particles | Jun 15, 2009 | Issued |
Array
(
[id] => 5569857
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[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/484618 | Method of manufacturing semiconductor device with offset sidewall structure | Jun 14, 2009 | Issued |
Array
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Array
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[id] => 7518777
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[patent_title] => 'Quantum dot memory'
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Array
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[patent_title] => 'FLASH MEMORY DEVICES COMPRISING PILLAR PATTERNS AND METHODS OF FABRICATING THE SAME'
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Array
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Array
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Array
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