Search

David A. Lambertson

Examiner (ID: 17494)

Most Active Art Unit
1636
Art Unit(s)
1636
Total Applications
261
Issued Applications
92
Pending Applications
86
Abandoned Applications
83

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1005349 [patent_doc_number] => 06905944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Sacrificial collar method for improved deep trench processing' [patent_app_type] => utility [patent_app_number] => 10/249798 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905944.pdf [firstpage_image] =>[orig_patent_app_number] => 10249798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249798
Sacrificial collar method for improved deep trench processing May 7, 2003 Issued
Array ( [id] => 6664234 [patent_doc_number] => 20030203560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof' [patent_app_type] => new [patent_app_number] => 10/421292 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5277 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203560.pdf [firstpage_image] =>[orig_patent_app_number] => 10421292 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421292
CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof Apr 22, 2003 Issued
Array ( [id] => 1033430 [patent_doc_number] => 06874898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'THIN FILM APPARATUS, A MANUFACTURING METHOD OF THE THIN FILM APPARATUS, AN ACTIVE MATRIX SUBSTRATE, A MANUFACTURING METHOD OF THE ACTIVE MATRIX SUBSTRATE, AND AN ELECTRO-OPTICAL APPARATUS HAVING THE ACTIVE MATRIX SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 10/418109 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 12713 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/874/06874898.pdf [firstpage_image] =>[orig_patent_app_number] => 10418109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418109
THIN FILM APPARATUS, A MANUFACTURING METHOD OF THE THIN FILM APPARATUS, AN ACTIVE MATRIX SUBSTRATE, A MANUFACTURING METHOD OF THE ACTIVE MATRIX SUBSTRATE, AND AN ELECTRO-OPTICAL APPARATUS HAVING THE ACTIVE MATRIX SUBSTRATE Apr 17, 2003 Issued
Array ( [id] => 1097460 [patent_doc_number] => 06822311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'DC or AC electric field assisted anneal' [patent_app_type] => B2 [patent_app_number] => 10/413301 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9862 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822311.pdf [firstpage_image] =>[orig_patent_app_number] => 10413301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/413301
DC or AC electric field assisted anneal Apr 14, 2003 Issued
Array ( [id] => 766375 [patent_doc_number] => 07008881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method for forming silicon epitaxial layer' [patent_app_type] => utility [patent_app_number] => 10/480789 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5689 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/008/07008881.pdf [firstpage_image] =>[orig_patent_app_number] => 10480789 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/480789
Method for forming silicon epitaxial layer Apr 8, 2003 Issued
Array ( [id] => 972125 [patent_doc_number] => 06936510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Semiconductor device with self-aligned contact and its manufacture' [patent_app_type] => utility [patent_app_number] => 10/388454 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 76 [patent_no_of_words] => 16551 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936510.pdf [firstpage_image] =>[orig_patent_app_number] => 10388454 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388454
Semiconductor device with self-aligned contact and its manufacture Mar 16, 2003 Issued
Array ( [id] => 985469 [patent_doc_number] => 06924197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source' [patent_app_type] => utility [patent_app_number] => 10/378568 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3880 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924197.pdf [firstpage_image] =>[orig_patent_app_number] => 10378568 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/378568
Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source Mar 2, 2003 Issued
Array ( [id] => 1002348 [patent_doc_number] => 06908802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/377971 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2558 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/908/06908802.pdf [firstpage_image] =>[orig_patent_app_number] => 10377971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/377971
Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same Feb 26, 2003 Issued
Array ( [id] => 1046733 [patent_doc_number] => 06864127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/357333 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 51 [patent_no_of_words] => 10942 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864127.pdf [firstpage_image] =>[orig_patent_app_number] => 10357333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357333
Semiconductor device and method of fabricating the same Feb 3, 2003 Issued
Array ( [id] => 790556 [patent_doc_number] => 06984576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-10 [patent_title] => 'Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip' [patent_app_type] => utility [patent_app_number] => 10/356800 [patent_app_country] => US [patent_app_date] => 2003-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 118 [patent_figures_cnt] => 353 [patent_no_of_words] => 23372 [patent_no_of_claims] => 300 [patent_no_of_ind_claims] => 27 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/984/06984576.pdf [firstpage_image] =>[orig_patent_app_number] => 10356800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356800
Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip Jan 31, 2003 Issued
Array ( [id] => 963596 [patent_doc_number] => 06949408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-27 [patent_title] => 'Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps' [patent_app_type] => utility [patent_app_number] => 10/356372 [patent_app_country] => US [patent_app_date] => 2003-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 89 [patent_no_of_words] => 13478 [patent_no_of_claims] => 300 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/949/06949408.pdf [firstpage_image] =>[orig_patent_app_number] => 10356372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356372
Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps Jan 31, 2003 Issued
Array ( [id] => 1012692 [patent_doc_number] => 06897163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method for depositing a low dielectric constant film' [patent_app_type] => utility [patent_app_number] => 10/355379 [patent_app_country] => US [patent_app_date] => 2003-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897163.pdf [firstpage_image] =>[orig_patent_app_number] => 10355379 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/355379
Method for depositing a low dielectric constant film Jan 30, 2003 Issued
Array ( [id] => 1105065 [patent_doc_number] => 06812164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method and apparatus for ionization film formation' [patent_app_type] => B2 [patent_app_number] => 10/350019 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6831 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812164.pdf [firstpage_image] =>[orig_patent_app_number] => 10350019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/350019
Method and apparatus for ionization film formation Jan 23, 2003 Issued
Array ( [id] => 1118153 [patent_doc_number] => 06801437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Electronic organic substrate' [patent_app_type] => B2 [patent_app_number] => 10/347759 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 12 [patent_no_of_words] => 2274 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801437.pdf [firstpage_image] =>[orig_patent_app_number] => 10347759 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/347759
Electronic organic substrate Jan 20, 2003 Issued
Array ( [id] => 7446349 [patent_doc_number] => 20040009677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Method for forming a thin film, methods for forming a gate electrode and transistor using the same, and a gate electrode manufactured using the same' [patent_app_type] => new [patent_app_number] => 10/337298 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4476 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20040009677.pdf [firstpage_image] =>[orig_patent_app_number] => 10337298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337298
Method for forming a thin film, methods for forming a gate electrode and transistor using the same, and a gate electrode manufactured using the same Jan 6, 2003 Issued
Array ( [id] => 1046796 [patent_doc_number] => 06864191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Hydrogen barrier layer and method for fabricating semiconductor device having the same' [patent_app_type] => utility [patent_app_number] => 10/329689 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3029 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864191.pdf [firstpage_image] =>[orig_patent_app_number] => 10329689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329689
Hydrogen barrier layer and method for fabricating semiconductor device having the same Dec 26, 2002 Issued
Array ( [id] => 1188869 [patent_doc_number] => 06734100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method of forming ruthenium thin film using plasma enhanced process' [patent_app_type] => B2 [patent_app_number] => 10/326769 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734100.pdf [firstpage_image] =>[orig_patent_app_number] => 10326769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/326769
Method of forming ruthenium thin film using plasma enhanced process Dec 19, 2002 Issued
Array ( [id] => 6659748 [patent_doc_number] => 20030134511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method for depositing metal film through chemical vapor deposition process' [patent_app_type] => new [patent_app_number] => 10/321729 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5293 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134511.pdf [firstpage_image] =>[orig_patent_app_number] => 10321729 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/321729
Method for depositing metal film through chemical vapor deposition process Dec 17, 2002 Issued
Array ( [id] => 6761455 [patent_doc_number] => 20030124817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Apparatus for fabricating compound semiconductor device' [patent_app_type] => new [patent_app_number] => 10/318768 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6634 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124817.pdf [firstpage_image] =>[orig_patent_app_number] => 10318768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318768
Apparatus for fabricating compound semiconductor device Dec 12, 2002 Issued
Array ( [id] => 6711196 [patent_doc_number] => 20030170945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Radical processing of a sub-nanometer insulation film' [patent_app_type] => new [patent_app_number] => 10/310949 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 75 [patent_no_of_words] => 34858 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20030170945.pdf [firstpage_image] =>[orig_patent_app_number] => 10310949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310949
Radical processing of a sub-nanometer insulation film Dec 5, 2002 Issued
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