Search

David A. Reifsnyder

Examiner (ID: 5560, Phone: (571)272-1145 , Office: P/1778 )

Most Active Art Unit
1723
Art Unit(s)
1778, 2899, 1776, 1723, 1306, 1797
Total Applications
2074
Issued Applications
1659
Pending Applications
148
Abandoned Applications
274

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18166682 [patent_doc_number] => 20230033286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => RECEIVER RECEIVING MULTI-LEVEL SIGNAL, MEMORY DEVICE INCLUDING THE SAME AND METHOD OF RECEIVING DATA USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/962992 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962992
Receiver receiving multi-level signal, memory device including the same and method of receiving data using the same Oct 9, 2022 Issued
Array ( [id] => 18168085 [patent_doc_number] => 20230034695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/961661 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961661
Semiconductor memory device and operating method thereof Oct 6, 2022 Issued
Array ( [id] => 19070817 [patent_doc_number] => 20240105243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => CLOCK QUALIFIER ENHANCEMENT FOR EXTERNAL DOUBLE DATA RATE MEMORY INTERFACES [patent_app_type] => utility [patent_app_number] => 17/954852 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954852
Clock qualifier enhancement for external double data rate memory interfaces Sep 27, 2022 Issued
Array ( [id] => 18142884 [patent_doc_number] => 20230016728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => On-Die Termination of Address and Command Signals [patent_app_type] => utility [patent_app_number] => 17/954223 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954223
On-die termination of address and command signals Sep 26, 2022 Issued
Array ( [id] => 19376457 [patent_doc_number] => 12068035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Memory, programming method therefor and memory system [patent_app_type] => utility [patent_app_number] => 17/944658 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 15933 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944658
Memory, programming method therefor and memory system Sep 13, 2022 Issued
Array ( [id] => 19414517 [patent_doc_number] => 12080351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Using non-segregated cells as drain-side select gates for sub-blocks in a memory device [patent_app_type] => utility [patent_app_number] => 17/944940 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944940
Using non-segregated cells as drain-side select gates for sub-blocks in a memory device Sep 13, 2022 Issued
Array ( [id] => 18312288 [patent_doc_number] => 20230116188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => RECEIVER WITH PIPELINE STRUCTURE FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/943448 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943448
Receiver with pipeline structure for receiving multi-level signal and memory device including the same Sep 12, 2022 Issued
Array ( [id] => 18112673 [patent_doc_number] => 20230005553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => INTERVALLIC DYNAMIC START VOLTAGE AND PROGRAM VERIFY SAMPLING IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/940338 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940338
Intervallic dynamic start voltage and program verify sampling in a memory sub-system Sep 7, 2022 Issued
Array ( [id] => 18561476 [patent_doc_number] => 11726719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Compound feature generation in classification of error rate of data retrieved from memory cells [patent_app_type] => utility [patent_app_number] => 17/939812 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 12462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939812
Compound feature generation in classification of error rate of data retrieved from memory cells Sep 6, 2022 Issued
Array ( [id] => 20117455 [patent_doc_number] => 12367161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Individually addressing memory devices disconnected from a data bus [patent_app_type] => utility [patent_app_number] => 17/929643 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929643
Individually addressing memory devices disconnected from a data bus Sep 1, 2022 Issued
Array ( [id] => 19356735 [patent_doc_number] => 12057190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Determining read voltage offset in memory devices [patent_app_type] => utility [patent_app_number] => 17/897438 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897438
Determining read voltage offset in memory devices Aug 28, 2022 Issued
Array ( [id] => 20080594 [patent_doc_number] => 12354669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Discharge circuits [patent_app_type] => utility [patent_app_number] => 17/897448 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2858 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897448
Discharge circuits Aug 28, 2022 Issued
Array ( [id] => 19356712 [patent_doc_number] => 12057167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Padding in flash memory blocks [patent_app_type] => utility [patent_app_number] => 17/897184 [patent_app_country] => US [patent_app_date] => 2022-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897184
Padding in flash memory blocks Aug 27, 2022 Issued
Array ( [id] => 18179075 [patent_doc_number] => 20230039804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => PHYSICAL UNCLONABLE FUNCTION WITH NAND MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/895693 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895693
Physical unclonable function with NAND memory array Aug 24, 2022 Issued
Array ( [id] => 19427952 [patent_doc_number] => 12087380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Memory, chip, and method for storing repair information of memory [patent_app_type] => utility [patent_app_number] => 17/894233 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10749 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894233
Memory, chip, and method for storing repair information of memory Aug 23, 2022 Issued
Array ( [id] => 19007396 [patent_doc_number] => 20240071467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/893654 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893654
Word line drivers for multiple-die memory devices Aug 22, 2022 Issued
Array ( [id] => 19110210 [patent_doc_number] => 11963343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Semiconductor device and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/892190 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 16598 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892190
Semiconductor device and operation method thereof Aug 21, 2022 Issued
Array ( [id] => 18990834 [patent_doc_number] => 20240062803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/890974 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890974
Apparatuses and methods for a per-DRAM addressability synchronizer circuit Aug 17, 2022 Issued
Array ( [id] => 18304253 [patent_doc_number] => 11626165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 17/888743 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888743
Memory device Aug 15, 2022 Issued
Array ( [id] => 18455875 [patent_doc_number] => 20230197156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => NON-VOLATILE MEMORY CELL AND NON-VOLATILE MEMORY CELL ARRAY [patent_app_type] => utility [patent_app_number] => 17/888526 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888526
Non-volatile memory cell and non-volatile memory cell array Aug 15, 2022 Issued
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