Search

David A. Zarneke

Examiner (ID: 8778, Phone: (571)272-1937 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2891, 2812, 2829, 2827
Total Applications
2297
Issued Applications
1864
Pending Applications
130
Abandoned Applications
332

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20590666 [patent_doc_number] => 20260076267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => 3D INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 19/384467 [patent_app_country] => US [patent_app_date] => 2025-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19384467 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/384467
3D INTEGRATED CIRCUIT PACKAGE Nov 9, 2025 Pending
Array ( [id] => 20224683 [patent_doc_number] => 20250287614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 19/214066 [patent_app_country] => US [patent_app_date] => 2025-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19214066 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/214066
COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE May 20, 2025 Pending
Array ( [id] => 20632124 [patent_doc_number] => 20260096416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => Power Grid Architecture [patent_app_type] => utility [patent_app_number] => 19/072630 [patent_app_country] => US [patent_app_date] => 2025-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19072630 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/072630
Power Grid Architecture Mar 5, 2025 Pending
Array ( [id] => 19845812 [patent_doc_number] => 20250091163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => PHOTONIC INTEGRATED CIRCUIT CHIP FACET PREPARATION VIA LASER-BASED DICING [patent_app_type] => utility [patent_app_number] => 18/888707 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/888707
PHOTONIC INTEGRATED CIRCUIT CHIP FACET PREPARATION VIA LASER-BASED DICING Sep 17, 2024 Pending
Array ( [id] => 19688147 [patent_doc_number] => 20250006692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => Method for Packaging Stacking Flip Chip [patent_app_type] => utility [patent_app_number] => 18/884085 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18884085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/884085
Method for packaging stacking flip chip Sep 11, 2024 Issued
Array ( [id] => 20532341 [patent_doc_number] => 12550796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Electronic package and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 18/826815 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826815
Electronic package and fabricating method thereof Sep 5, 2024 Issued
Array ( [id] => 20153369 [patent_doc_number] => 20250253207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => FABRICATION METHODS AND STRUCTURES FOR LIQUID COOLING CHANNEL CHIP [patent_app_type] => utility [patent_app_number] => 18/788853 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788853
FABRICATION METHODS AND STRUCTURES FOR LIQUID COOLING CHANNEL CHIP Jul 29, 2024 Pending
Array ( [id] => 20139439 [patent_doc_number] => 20250246483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => METHOD FOR FORMING DIELECTRIC LINERS ON THROUGH GLASS VIAS [patent_app_type] => utility [patent_app_number] => 18/775475 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775475 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775475
METHOD FOR FORMING DIELECTRIC LINERS ON THROUGH GLASS VIAS Jul 16, 2024 Pending
Array ( [id] => 19546547 [patent_doc_number] => 20240363583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => METHODS OF FORMING WIRE INTERCONNECT STRUCTURES AND RELATED WIRE BONDING TOOLS [patent_app_type] => utility [patent_app_number] => 18/765653 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765653
Methods of forming wire interconnect structures and related wire bonding tools Jul 7, 2024 Issued
Array ( [id] => 19500379 [patent_doc_number] => 20240339397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => INTERCONNECTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/746055 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746055 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746055
Interconnection structure Jun 17, 2024 Issued
Array ( [id] => 19500342 [patent_doc_number] => 20240339360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES [patent_app_type] => utility [patent_app_number] => 18/744493 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744493
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES Jun 13, 2024 Abandoned
Array ( [id] => 19484290 [patent_doc_number] => 20240332332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => TRENCH ISOLATION STRUCTURE FOR SCALED PIXEL REGION [patent_app_type] => utility [patent_app_number] => 18/733947 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733947
Trench isolation structure for scaled pixel region Jun 4, 2024 Issued
Array ( [id] => 19758204 [patent_doc_number] => 20250046769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/665893 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665893 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665893
SEMICONDUCTOR PACKAGE May 15, 2024 Pending
Array ( [id] => 19436082 [patent_doc_number] => 20240304580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => BONDING STRUCTURE AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/663124 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663124
BONDING STRUCTURE AND METHOD THEREOF May 13, 2024 Pending
Array ( [id] => 20553296 [patent_doc_number] => 12564111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Double-sided integrated circuit module having an exposed semiconductor die [patent_app_type] => utility [patent_app_number] => 18/657968 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657968
Double-sided integrated circuit module having an exposed semiconductor die May 7, 2024 Issued
Array ( [id] => 19698521 [patent_doc_number] => 20250017066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/657660 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657660 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657660
DISPLAY DEVICE May 6, 2024 Pending
Array ( [id] => 20352852 [patent_doc_number] => 20250349704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => THROUGH DIELECTRIC VIA [patent_app_type] => utility [patent_app_number] => 18/657165 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657165
THROUGH DIELECTRIC VIA May 6, 2024 Pending
Array ( [id] => 19421019 [patent_doc_number] => 20240297143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => BONDING TOOL AND BONDING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/654016 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654016 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654016
Bonding tool and bonding method thereof May 2, 2024 Issued
Array ( [id] => 19407295 [patent_doc_number] => 20240290806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => ABSORPTION ENHANCEMENT STRUCTURE TO INCREASE QUANTUM EFFICIENCY OF IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 18/650172 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650172
Absorption enhancement structure to increase quantum efficiency of image sensor Apr 29, 2024 Issued
Array ( [id] => 19384767 [patent_doc_number] => 20240274637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => IMAGE SENSOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/643860 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643860
Image sensor device and manufacturing method thereof Apr 22, 2024 Issued
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