
David A. Zarneke
Examiner (ID: 17793)
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2829, 2812, 2827, 2891 |
| Total Applications | 2255 |
| Issued Applications | 1829 |
| Pending Applications | 145 |
| Abandoned Applications | 326 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19796382
[patent_doc_number] => 12237354
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-25
[patent_title] => Chip package and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/683917
[patent_app_country] => US
[patent_app_date] => 2022-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 26
[patent_no_of_words] => 8139
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683917
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/683917 | Chip package and method for forming the same | Feb 28, 2022 | Issued |
Array
(
[id] => 19093989
[patent_doc_number] => 11955454
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-09
[patent_title] => Wafer bonding apparatus and method
[patent_app_type] => utility
[patent_app_number] => 17/681161
[patent_app_country] => US
[patent_app_date] => 2022-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 26
[patent_no_of_words] => 13560
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681161
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/681161 | Wafer bonding apparatus and method | Feb 24, 2022 | Issued |
Array
(
[id] => 19436096
[patent_doc_number] => 20240304594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => BONDING METHOD, SUBSTRATE BONDING DEVICE, AND SUBSTRATE BONDING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/546590
[patent_app_country] => US
[patent_app_date] => 2022-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20781
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18546590
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/546590 | BONDING METHOD, SUBSTRATE BONDING DEVICE, AND SUBSTRATE BONDING SYSTEM | Feb 23, 2022 | Pending |
Array
(
[id] => 18165969
[patent_doc_number] => 20230032570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => BONDING TOOL AND BONDING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/672285
[patent_app_country] => US
[patent_app_date] => 2022-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8173
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672285
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/672285 | Bonding tool and bonding method thereof | Feb 14, 2022 | Issued |
Array
(
[id] => 19596999
[patent_doc_number] => 12154852
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-26
[patent_title] => Interconnection structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/670520
[patent_app_country] => US
[patent_app_date] => 2022-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 7175
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670520
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/670520 | Interconnection structure and manufacturing method thereof | Feb 13, 2022 | Issued |
Array
(
[id] => 19487332
[patent_doc_number] => 12107057
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Method for permanent connection of two metal surfaces
[patent_app_type] => utility
[patent_app_number] => 17/669417
[patent_app_country] => US
[patent_app_date] => 2022-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 4722
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669417
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/669417 | Method for permanent connection of two metal surfaces | Feb 10, 2022 | Issued |
Array
(
[id] => 18540831
[patent_doc_number] => 20230245942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRAL HEAT SLUG
[patent_app_type] => utility
[patent_app_number] => 17/589761
[patent_app_country] => US
[patent_app_date] => 2022-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8455
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589761
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/589761 | SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRAL HEAT SLUG | Jan 30, 2022 | Pending |
Array
(
[id] => 18540831
[patent_doc_number] => 20230245942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRAL HEAT SLUG
[patent_app_type] => utility
[patent_app_number] => 17/589761
[patent_app_country] => US
[patent_app_date] => 2022-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8455
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589761
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/589761 | SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRAL HEAT SLUG | Jan 30, 2022 | Pending |
Array
(
[id] => 19033142
[patent_doc_number] => 20240082957
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/261520
[patent_app_country] => US
[patent_app_date] => 2022-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8552
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18261520
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/261520 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD | Jan 4, 2022 | Pending |
Array
(
[id] => 18473206
[patent_doc_number] => 20230207494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => SINGLE LAYER AND MULTILAYER MAGNETIC INDUCTORS BETWEEN SUBSTRATE CORES
[patent_app_type] => utility
[patent_app_number] => 17/561726
[patent_app_country] => US
[patent_app_date] => 2021-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12854
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561726
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/561726 | SINGLE LAYER AND MULTILAYER MAGNETIC INDUCTORS BETWEEN SUBSTRATE CORES | Dec 23, 2021 | Pending |
Array
(
[id] => 18473044
[patent_doc_number] => 20230207332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => DIELECTRIC FILM COATING FOR THROUGH GLASS VIAS AND PLANE SURFACE ROUGHNESS MITIGATION
[patent_app_type] => utility
[patent_app_number] => 17/557961
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7334
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557961
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/557961 | Dielectric film coating for through glass vias and plane surface roughness mitigation | Dec 20, 2021 | Issued |
Array
(
[id] => 18473044
[patent_doc_number] => 20230207332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => DIELECTRIC FILM COATING FOR THROUGH GLASS VIAS AND PLANE SURFACE ROUGHNESS MITIGATION
[patent_app_type] => utility
[patent_app_number] => 17/557961
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7334
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557961
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/557961 | Dielectric film coating for through glass vias and plane surface roughness mitigation | Dec 20, 2021 | Issued |
Array
(
[id] => 17709071
[patent_doc_number] => 20220209079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => LIGHT-EMITTING MODULE AND METHOD OF MANUFACTURING LIGHT-EMITTING MODULE
[patent_app_type] => utility
[patent_app_number] => 17/557235
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12234
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557235
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/557235 | LIGHT-EMITTING MODULE AND METHOD OF MANUFACTURING LIGHT-EMITTING MODULE | Dec 20, 2021 | Issued |
Array
(
[id] => 17709071
[patent_doc_number] => 20220209079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => LIGHT-EMITTING MODULE AND METHOD OF MANUFACTURING LIGHT-EMITTING MODULE
[patent_app_type] => utility
[patent_app_number] => 17/557235
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12234
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557235
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/557235 | LIGHT-EMITTING MODULE AND METHOD OF MANUFACTURING LIGHT-EMITTING MODULE | Dec 20, 2021 | Issued |
Array
(
[id] => 18623854
[patent_doc_number] => 11756910
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Package for power electronics
[patent_app_type] => utility
[patent_app_number] => 17/557322
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5135
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557322
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/557322 | Package for power electronics | Dec 20, 2021 | Issued |
Array
(
[id] => 17536822
[patent_doc_number] => 20220115431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => PIXEL FORMATION METHOD
[patent_app_type] => utility
[patent_app_number] => 17/556141
[patent_app_country] => US
[patent_app_date] => 2021-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7804
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556141
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/556141 | Pixel formation method | Dec 19, 2021 | Issued |
Array
(
[id] => 19356974
[patent_doc_number] => 12057431
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-06
[patent_title] => Methods of forming wire interconnect structures and related wire bonding tools
[patent_app_type] => utility
[patent_app_number] => 17/550729
[patent_app_country] => US
[patent_app_date] => 2021-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 2974
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550729
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/550729 | Methods of forming wire interconnect structures and related wire bonding tools | Dec 13, 2021 | Issued |
Array
(
[id] => 17551697
[patent_doc_number] => 20220123039
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/547787
[patent_app_country] => US
[patent_app_date] => 2021-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11324
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547787
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/547787 | Semiconductor device | Dec 9, 2021 | Issued |
Array
(
[id] => 17509062
[patent_doc_number] => 20220102165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => CONDUCTIVE VIA STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/643190
[patent_app_country] => US
[patent_app_date] => 2021-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3214
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643190
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/643190 | CONDUCTIVE VIA STRUCTURE | Dec 7, 2021 | Abandoned |
Array
(
[id] => 19796464
[patent_doc_number] => 12237436
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-25
[patent_title] => Welding method for welding strip of back-contact solar cell chip
[patent_app_type] => utility
[patent_app_number] => 17/457668
[patent_app_country] => US
[patent_app_date] => 2021-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 26
[patent_no_of_words] => 3918
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457668
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/457668 | Welding method for welding strip of back-contact solar cell chip | Dec 4, 2021 | Issued |