
David A Zarneke
Examiner (ID: 17793, Phone: (571)272-1937 , Office: P/2891 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2829, 2812, 2827, 2891 |
| Total Applications | 2255 |
| Issued Applications | 1829 |
| Pending Applications | 145 |
| Abandoned Applications | 326 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5005063
[patent_doc_number] => 20070202633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-30
[patent_title] => 'Semiconductor package and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/651708
[patent_app_country] => US
[patent_app_date] => 2007-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2518
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[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20070202633.pdf
[firstpage_image] =>[orig_patent_app_number] => 11651708
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/651708 | Semiconductor package and method for fabricating the same | Jan 8, 2007 | Abandoned |
Array
(
[id] => 4474495
[patent_doc_number] => 07867829
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-11
[patent_title] => 'Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/618038
[patent_app_country] => US
[patent_app_date] => 2006-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1843
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[patent_maintenance] => 1
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[pdf_file] => patents/07/867/07867829.pdf
[firstpage_image] =>[orig_patent_app_number] => 11618038
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618038 | Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device | Dec 28, 2006 | Issued |
Array
(
[id] => 173765
[patent_doc_number] => 07659144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-09
[patent_title] => 'Semiconductor device and manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/618188
[patent_app_country] => US
[patent_app_date] => 2006-12-29
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[patent_drawing_sheets_cnt] => 28
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[pdf_file] => patents/07/659/07659144.pdf
[firstpage_image] =>[orig_patent_app_number] => 11618188
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618188 | Semiconductor device and manufacturing the same | Dec 28, 2006 | Issued |
Array
(
[id] => 4752600
[patent_doc_number] => 20080160675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Microelectronic package with thermal access'
[patent_app_type] => utility
[patent_app_number] => 11/648719
[patent_app_country] => US
[patent_app_date] => 2006-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[firstpage_image] =>[orig_patent_app_number] => 11648719
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648719 | Microelectronic package with thermal access | Dec 28, 2006 | Issued |
Array
(
[id] => 4752599
[patent_doc_number] => 20080160674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING MULTIPLE DIE REDISTRIBUTION LAYER'
[patent_app_type] => utility
[patent_app_number] => 11/617689
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0160/20080160674.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617689
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617689 | Method of making a semiconductor device having multiple die redistribution layer | Dec 27, 2006 | Issued |
Array
(
[id] => 4752676
[patent_doc_number] => 20080160751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'MICROELECTRONIC DIE INCLUDING SOLDER CAPS ON BUMPING SITES THEREOF AND METHOD OF MAKING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/617589
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 11617589
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617589 | MICROELECTRONIC DIE INCLUDING SOLDER CAPS ON BUMPING SITES THEREOF AND METHOD OF MAKING SAME | Dec 27, 2006 | Abandoned |
Array
(
[id] => 4752595
[patent_doc_number] => 20080160670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'PHYSICAL ALIGNMENT FEATURES ON INTEGRATED CIRCUIT DEVICES FOR ACCURATE DIE-IN-SUBSTRATE EMBEDDING'
[patent_app_type] => utility
[patent_app_number] => 11/616479
[patent_app_country] => US
[patent_app_date] => 2006-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3407
[patent_no_of_claims] => 15
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[pdf_file] => publications/A1/0160/20080160670.pdf
[firstpage_image] =>[orig_patent_app_number] => 11616479
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616479 | PHYSICAL ALIGNMENT FEATURES ON INTEGRATED CIRCUIT DEVICES FOR ACCURATE DIE-IN-SUBSTRATE EMBEDDING | Dec 26, 2006 | Abandoned |
Array
(
[id] => 4879817
[patent_doc_number] => 20080153200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Stacked semiconductor components'
[patent_app_type] => utility
[patent_app_number] => 11/644329
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4714
[patent_no_of_claims] => 26
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[pdf_file] => publications/A1/0153/20080153200.pdf
[firstpage_image] =>[orig_patent_app_number] => 11644329
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644329 | Stacked semiconductor components | Dec 21, 2006 | Abandoned |
Array
(
[id] => 7689300
[patent_doc_number] => 20070105398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/644236
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 5771
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[pdf_file] => publications/A1/0105/20070105398.pdf
[firstpage_image] =>[orig_patent_app_number] => 11644236
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644236 | Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device | Dec 21, 2006 | Issued |
Array
(
[id] => 5250641
[patent_doc_number] => 20070132097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'Projected contact structures for engaging bumped semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/644333
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0132/20070132097.pdf
[firstpage_image] =>[orig_patent_app_number] => 11644333
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644333 | Projected contact structures for engaging bumped semiconductor devices | Dec 21, 2006 | Abandoned |
Array
(
[id] => 5091785
[patent_doc_number] => 20070113394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-24
[patent_title] => 'AIR SOCKET FOR TESTING INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 11/614609
[patent_app_country] => US
[patent_app_date] => 2006-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[firstpage_image] =>[orig_patent_app_number] => 11614609
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/614609 | AIR SOCKET FOR TESTING INTEGRATED CIRCUITS | Dec 20, 2006 | Abandoned |
Array
(
[id] => 5019571
[patent_doc_number] => 20070145537
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
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[patent_app_number] => 11/614748
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Array
(
[id] => 5031757
[patent_doc_number] => 20070096296
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[patent_title] => 'Manufacture of mountable capped chips'
[patent_app_type] => utility
[patent_app_number] => 11/642354
[patent_app_country] => US
[patent_app_date] => 2006-12-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/642354 | Manufacture of mountable capped chips | Dec 19, 2006 | Issued |
Array
(
[id] => 5019638
[patent_doc_number] => 20070145604
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[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'CHIP STRUCTURE AND CHIP MANUFACTURING PROCESS'
[patent_app_type] => utility
[patent_app_number] => 11/610319
[patent_app_country] => US
[patent_app_date] => 2006-12-13
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Array
(
[id] => 4977443
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[patent_title] => 'Method for forming metal bumps'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/635498 | Method for forming metal bumps | Dec 7, 2006 | Issued |
Array
(
[id] => 267061
[patent_doc_number] => 07566586
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[patent_issue_date] => 2009-07-28
[patent_title] => 'Method of manufacturing a semiconductor device'
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Array
(
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[patent_title] => 'Cutting method for substrate and cutting apparatus therefor'
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Array
(
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Array
(
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Array
(
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[patent_title] => 'Fan out type wafer level package structure and method of the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/595970 | Fan out type wafer level package structure and method of the same | Nov 12, 2006 | Abandoned |