Search

David A Zarneke

Examiner (ID: 17793, Phone: (571)272-1937 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2829, 2812, 2827, 2891
Total Applications
2255
Issued Applications
1829
Pending Applications
145
Abandoned Applications
326

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 285392 [patent_doc_number] => 07550318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Interconnect for improved die to substrate electrical coupling' [patent_app_type] => utility [patent_app_number] => 11/502679 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/550/07550318.pdf [firstpage_image] =>[orig_patent_app_number] => 11502679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502679
Interconnect for improved die to substrate electrical coupling Aug 10, 2006 Issued
Array ( [id] => 5685972 [patent_doc_number] => 20060284287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'TWO-POLE SMT MINIATURE HOUSING FOR SEMICONDUCTOR COMPONENTS AND METHOD FOR THE MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 11/463127 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1211 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20060284287.pdf [firstpage_image] =>[orig_patent_app_number] => 11463127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463127
Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof Aug 7, 2006 Issued
Array ( [id] => 482762 [patent_doc_number] => 07220673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Method for depositing tungsten-containing layers by vapor deposition techniques' [patent_app_type] => utility [patent_app_number] => 11/461909 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3960 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220673.pdf [firstpage_image] =>[orig_patent_app_number] => 11461909 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461909
Method for depositing tungsten-containing layers by vapor deposition techniques Aug 1, 2006 Issued
Array ( [id] => 387012 [patent_doc_number] => 07304381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Package and method for attaching an integrated heat spreader' [patent_app_type] => utility [patent_app_number] => 11/461803 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4215 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304381.pdf [firstpage_image] =>[orig_patent_app_number] => 11461803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461803
Package and method for attaching an integrated heat spreader Aug 1, 2006 Issued
Array ( [id] => 5625429 [patent_doc_number] => 20060263934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'CHIP-TYPE MICRO-CONNECTOR AND METHOD OF PACKAGING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/461458 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2668 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20060263934.pdf [firstpage_image] =>[orig_patent_app_number] => 11461458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461458
CHIP-TYPE MICRO-CONNECTOR AND METHOD OF PACKAGING THE SAME Jul 31, 2006 Abandoned
Array ( [id] => 5054458 [patent_doc_number] => 20070057379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/495718 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2986 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057379.pdf [firstpage_image] =>[orig_patent_app_number] => 11495718 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495718
Method of manufacturing a semiconductor device Jul 30, 2006 Issued
Array ( [id] => 4695601 [patent_doc_number] => 20080217785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Semiconductor Device with Grounding Structure' [patent_app_type] => utility [patent_app_number] => 11/997240 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4092 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217785.pdf [firstpage_image] =>[orig_patent_app_number] => 11997240 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/997240
Semiconductor device with grounding structure Jul 30, 2006 Issued
Array ( [id] => 5520221 [patent_doc_number] => 20090028202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Nitride light emitting device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/919639 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20090028202.pdf [firstpage_image] =>[orig_patent_app_number] => 11919639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/919639
Nitride light emitting device and manufacturing method thereof Jul 30, 2006 Issued
Array ( [id] => 592918 [patent_doc_number] => 07436055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Packaging method of a plurality of chips stacked on each other and package structure thereof' [patent_app_type] => utility [patent_app_number] => 11/459919 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2659 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/436/07436055.pdf [firstpage_image] =>[orig_patent_app_number] => 11459919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459919
Packaging method of a plurality of chips stacked on each other and package structure thereof Jul 24, 2006 Issued
Array ( [id] => 5242414 [patent_doc_number] => 20070020909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Forming of conductive bumps for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/491838 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2082 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020909.pdf [firstpage_image] =>[orig_patent_app_number] => 11491838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/491838
Forming of conductive bumps for an integrated circuit Jul 23, 2006 Abandoned
Array ( [id] => 519881 [patent_doc_number] => 07193310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Stacking system and method' [patent_app_type] => utility [patent_app_number] => 11/489956 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3534 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193310.pdf [firstpage_image] =>[orig_patent_app_number] => 11489956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/489956
Stacking system and method Jul 19, 2006 Issued
Array ( [id] => 587839 [patent_doc_number] => 07446424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Interconnect structure for semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/458479 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3933 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446424.pdf [firstpage_image] =>[orig_patent_app_number] => 11458479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458479
Interconnect structure for semiconductor package Jul 18, 2006 Issued
Array ( [id] => 5056941 [patent_doc_number] => 20070059863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method of manufacturing quad flat non-leaded semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/486569 [patent_app_country] => US [patent_app_date] => 2006-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20070059863.pdf [firstpage_image] =>[orig_patent_app_number] => 11486569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486569
Method of manufacturing quad flat non-leaded semiconductor package Jul 13, 2006 Abandoned
Array ( [id] => 4801662 [patent_doc_number] => 20080013249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Method for Producing a Dielectric Layer for an Electronic Component' [patent_app_type] => utility [patent_app_number] => 11/457318 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6393 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20080013249.pdf [firstpage_image] =>[orig_patent_app_number] => 11457318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457318
Method for producing a dielectric layer for an electronic component Jul 12, 2006 Issued
Array ( [id] => 5659241 [patent_doc_number] => 20060249837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Integrated circuit cooling and insulating device and method' [patent_app_type] => utility [patent_app_number] => 11/482308 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4194 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20060249837.pdf [firstpage_image] =>[orig_patent_app_number] => 11482308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482308
Integrated circuit cooling and insulating device and method Jul 6, 2006 Issued
Array ( [id] => 326993 [patent_doc_number] => 07514767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Fan out type wafer level package structure and method of the same' [patent_app_type] => utility [patent_app_number] => 11/456141 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514767.pdf [firstpage_image] =>[orig_patent_app_number] => 11456141 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/456141
Fan out type wafer level package structure and method of the same Jul 6, 2006 Issued
Array ( [id] => 330452 [patent_doc_number] => 07510947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Method for wafer level packaging and fabricating cap structures' [patent_app_type] => utility [patent_app_number] => 11/428409 [patent_app_country] => US [patent_app_date] => 2006-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 1777 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/510/07510947.pdf [firstpage_image] =>[orig_patent_app_number] => 11428409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428409
Method for wafer level packaging and fabricating cap structures Jul 2, 2006 Issued
Array ( [id] => 4992320 [patent_doc_number] => 20070007664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'SEMICONDUCTOR PACKAGE WITH MOLDED BACK SIDE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/428169 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8255 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20070007664.pdf [firstpage_image] =>[orig_patent_app_number] => 11428169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428169
SEMICONDUCTOR PACKAGE WITH MOLDED BACK SIDE AND METHOD OF FABRICATING THE SAME Jun 29, 2006 Abandoned
Array ( [id] => 4932943 [patent_doc_number] => 20080003718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Singulation Process for Block-Molded Packages' [patent_app_type] => utility [patent_app_number] => 11/428079 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3020 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003718.pdf [firstpage_image] =>[orig_patent_app_number] => 11428079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428079
Singulation Process for Block-Molded Packages Jun 29, 2006 Abandoned
Array ( [id] => 103093 [patent_doc_number] => 07728398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Micro camera module and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/476160 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3008 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/728/07728398.pdf [firstpage_image] =>[orig_patent_app_number] => 11476160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/476160
Micro camera module and method of manufacturing the same Jun 27, 2006 Issued
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