Search

David A. Zarneke

Examiner (ID: 17793)

Most Active Art Unit
2891
Art Unit(s)
2829, 2812, 2827, 2891
Total Applications
2255
Issued Applications
1829
Pending Applications
145
Abandoned Applications
326

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5898356 [patent_doc_number] => 20060043589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Electronic device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/199158 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15200 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043589.pdf [firstpage_image] =>[orig_patent_app_number] => 11199158 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199158
Electronic device and method for fabricating the same Aug 8, 2005 Abandoned
Array ( [id] => 903050 [patent_doc_number] => 07335576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Method for precision integrated circuit die singulation using differential etch rates' [patent_app_type] => utility [patent_app_number] => 11/197828 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3401 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/335/07335576.pdf [firstpage_image] =>[orig_patent_app_number] => 11197828 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197828
Method for precision integrated circuit die singulation using differential etch rates Aug 4, 2005 Issued
Array ( [id] => 843516 [patent_doc_number] => 07387948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Structure and method of forming a semiconductor material wafer' [patent_app_type] => utility [patent_app_number] => 11/196338 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/387/07387948.pdf [firstpage_image] =>[orig_patent_app_number] => 11196338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196338
Structure and method of forming a semiconductor material wafer Aug 3, 2005 Issued
Array ( [id] => 5880987 [patent_doc_number] => 20060030070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Packaging structure and method of an image sensor module' [patent_app_type] => utility [patent_app_number] => 11/194669 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4420 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20060030070.pdf [firstpage_image] =>[orig_patent_app_number] => 11194669 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194669
Packaging structure and method of an image sensor module Aug 1, 2005 Issued
Array ( [id] => 5765707 [patent_doc_number] => 20050263803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Semiconductor device includes gate insulating film having a high dielectric constant' [patent_app_type] => utility [patent_app_number] => 11/193349 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4121 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263803.pdf [firstpage_image] =>[orig_patent_app_number] => 11193349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/193349
Semiconductor device includes gate insulating film having a high dielectric constant Jul 31, 2005 Issued
Array ( [id] => 5820628 [patent_doc_number] => 20060024941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method of forming metal interconnect of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/191518 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7557 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20060024941.pdf [firstpage_image] =>[orig_patent_app_number] => 11191518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191518
Method of forming metal interconnect of semiconductor device Jul 27, 2005 Abandoned
Array ( [id] => 356232 [patent_doc_number] => 07488668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions' [patent_app_type] => utility [patent_app_number] => 11/183739 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 12768 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488668.pdf [firstpage_image] =>[orig_patent_app_number] => 11183739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183739
Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions Jul 18, 2005 Issued
Array ( [id] => 5793640 [patent_doc_number] => 20060014321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Manufacturing method of semiconductor device and manufacturing method of lead frame' [patent_app_type] => utility [patent_app_number] => 11/181929 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7013 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20060014321.pdf [firstpage_image] =>[orig_patent_app_number] => 11181929 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181929
Manufacturing method of semiconductor device and manufacturing method of lead frame Jul 14, 2005 Issued
Array ( [id] => 5765858 [patent_doc_number] => 20050263870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'High density 3-D integrated circuit package' [patent_app_type] => utility [patent_app_number] => 11/179377 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1601 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263870.pdf [firstpage_image] =>[orig_patent_app_number] => 11179377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/179377
High density 3-D integrated circuit package Jul 11, 2005 Issued
Array ( [id] => 435826 [patent_doc_number] => 07262081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Fan out type wafer level package structure and method of the same' [patent_app_type] => utility [patent_app_number] => 11/169722 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3428 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262081.pdf [firstpage_image] =>[orig_patent_app_number] => 11169722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169722
Fan out type wafer level package structure and method of the same Jun 29, 2005 Issued
Array ( [id] => 5738557 [patent_doc_number] => 20060008948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Method of processing a semiconductor wafer for manufacture of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/172689 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2580 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20060008948.pdf [firstpage_image] =>[orig_patent_app_number] => 11172689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/172689
Method of processing a semiconductor wafer for manufacture of semiconductor device Jun 29, 2005 Issued
Array ( [id] => 390223 [patent_doc_number] => 07300819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Semiconductor device, method for mounting the same, and method for repairing the same' [patent_app_type] => utility [patent_app_number] => 11/168549 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 6980 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/300/07300819.pdf [firstpage_image] =>[orig_patent_app_number] => 11168549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/168549
Semiconductor device, method for mounting the same, and method for repairing the same Jun 28, 2005 Issued
Array ( [id] => 359671 [patent_doc_number] => 07485550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method for producing semiconductor elements' [patent_app_type] => utility [patent_app_number] => 11/166768 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485550.pdf [firstpage_image] =>[orig_patent_app_number] => 11166768 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/166768
Method for producing semiconductor elements Jun 23, 2005 Issued
Array ( [id] => 307833 [patent_doc_number] => 07531907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'System and method for forming serial numbers on HDD wafers' [patent_app_type] => utility [patent_app_number] => 11/151118 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2585 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531907.pdf [firstpage_image] =>[orig_patent_app_number] => 11151118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151118
System and method for forming serial numbers on HDD wafers Jun 12, 2005 Issued
Array ( [id] => 425129 [patent_doc_number] => 07271111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Shadow mask deposition of materials using reconfigurable shadow masks' [patent_app_type] => utility [patent_app_number] => 11/147508 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7964 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271111.pdf [firstpage_image] =>[orig_patent_app_number] => 11147508 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/147508
Shadow mask deposition of materials using reconfigurable shadow masks Jun 7, 2005 Issued
Array ( [id] => 449798 [patent_doc_number] => 07250663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Frame scale package using contact lines through the elements' [patent_app_type] => utility [patent_app_number] => 11/135558 [patent_app_country] => US [patent_app_date] => 2005-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1138 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250663.pdf [firstpage_image] =>[orig_patent_app_number] => 11135558 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/135558
Frame scale package using contact lines through the elements May 23, 2005 Issued
Array ( [id] => 7108531 [patent_doc_number] => 20050205984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Package structure with a retarding structure and method of making same' [patent_app_type] => utility [patent_app_number] => 11/134988 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2994 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20050205984.pdf [firstpage_image] =>[orig_patent_app_number] => 11134988 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134988
Package structure with a retarding structure and method of making same May 22, 2005 Issued
Array ( [id] => 7108527 [patent_doc_number] => 20050205980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Method of sensor packaging' [patent_app_type] => utility [patent_app_number] => 11/134709 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4938 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20050205980.pdf [firstpage_image] =>[orig_patent_app_number] => 11134709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134709
Method of sensor packaging May 19, 2005 Issued
Array ( [id] => 823980 [patent_doc_number] => 07405453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Incorporation of nitrogen into high k dielectric film' [patent_app_type] => utility [patent_app_number] => 11/132096 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 12319 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405453.pdf [firstpage_image] =>[orig_patent_app_number] => 11132096 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/132096
Incorporation of nitrogen into high k dielectric film May 16, 2005 Issued
Array ( [id] => 383059 [patent_doc_number] => 07307011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Structure and method for forming a dielectric chamber and electronic device including the dielectric chamber' [patent_app_type] => utility [patent_app_number] => 11/129325 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 3663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307011.pdf [firstpage_image] =>[orig_patent_app_number] => 11129325 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/129325
Structure and method for forming a dielectric chamber and electronic device including the dielectric chamber May 15, 2005 Issued
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