Search

David Armand Wiley

Examiner (ID: 5040)

Most Active Art Unit
2781
Art Unit(s)
2174, 2158, 2305, 2100, 2155, 3781, 2781, 2143, 2855
Total Applications
522
Issued Applications
399
Pending Applications
75
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4401801 [patent_doc_number] => 06279052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Dynamic sizing of FIFOs and packets in high speed serial bus applications' [patent_app_type] => 1 [patent_app_number] => 9/006511 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2554 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279052.pdf [firstpage_image] =>[orig_patent_app_number] => 006511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006511
Dynamic sizing of FIFOs and packets in high speed serial bus applications Jan 12, 1998 Issued
Array ( [id] => 4316694 [patent_doc_number] => 06199164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Information management system and apparatus using open network environment, and storage medium storing control program of apparatus and capable of being read by computer' [patent_app_type] => 1 [patent_app_number] => 9/005186 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 60 [patent_no_of_words] => 19257 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199164.pdf [firstpage_image] =>[orig_patent_app_number] => 005186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005186
Information management system and apparatus using open network environment, and storage medium storing control program of apparatus and capable of being read by computer Jan 8, 1998 Issued
Array ( [id] => 4155362 [patent_doc_number] => 06122676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Apparatus and method for transmitting and receiving data into and out of a universal serial bus device' [patent_app_type] => 1 [patent_app_number] => 9/004004 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5121 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122676.pdf [firstpage_image] =>[orig_patent_app_number] => 004004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004004
Apparatus and method for transmitting and receiving data into and out of a universal serial bus device Jan 6, 1998 Issued
Array ( [id] => 4318403 [patent_doc_number] => 06185699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method and apparatus providing system availability during DBMS restart recovery' [patent_app_type] => 1 [patent_app_number] => 9/003085 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5768 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185699.pdf [firstpage_image] =>[orig_patent_app_number] => 003085 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003085
Method and apparatus providing system availability during DBMS restart recovery Jan 4, 1998 Issued
Array ( [id] => 3968823 [patent_doc_number] => 05948076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method and system for changing peripheral component interconnect configuration registers' [patent_app_type] => 1 [patent_app_number] => 9/001615 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2757 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948076.pdf [firstpage_image] =>[orig_patent_app_number] => 001615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001615
Method and system for changing peripheral component interconnect configuration registers Dec 30, 1997 Issued
Array ( [id] => 4379287 [patent_doc_number] => 06192431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method and apparatus for configuring the pinout of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/001550 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4493 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192431.pdf [firstpage_image] =>[orig_patent_app_number] => 001550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001550
Method and apparatus for configuring the pinout of an integrated circuit Dec 30, 1997 Issued
Array ( [id] => 4239952 [patent_doc_number] => 06012116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Apparatus and method for controlling data, address, and enable buses within a microprocessor' [patent_app_type] => 1 [patent_app_number] => 9/001825 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6168 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012116.pdf [firstpage_image] =>[orig_patent_app_number] => 001825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001825
Apparatus and method for controlling data, address, and enable buses within a microprocessor Dec 30, 1997 Issued
Array ( [id] => 4426966 [patent_doc_number] => 06195761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method and apparatus for identifying and repairing mismatched data' [patent_app_type] => 1 [patent_app_number] => 9/001684 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12095 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195761.pdf [firstpage_image] =>[orig_patent_app_number] => 001684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001684
Method and apparatus for identifying and repairing mismatched data Dec 30, 1997 Issued
Array ( [id] => 4373485 [patent_doc_number] => 06202114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Spanning tree with fast link-failure convergence' [patent_app_type] => 1 [patent_app_number] => 9/002115 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 6576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202114.pdf [firstpage_image] =>[orig_patent_app_number] => 002115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002115
Spanning tree with fast link-failure convergence Dec 30, 1997 Issued
Array ( [id] => 4422661 [patent_doc_number] => 06233703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Automatic generation of evaluation order for a function block diagram and detection of any associated errors' [patent_app_type] => 1 [patent_app_number] => 9/002184 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4363 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233703.pdf [firstpage_image] =>[orig_patent_app_number] => 002184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002184
Automatic generation of evaluation order for a function block diagram and detection of any associated errors Dec 30, 1997 Issued
Array ( [id] => 4422591 [patent_doc_number] => 06233696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Data verification and repair in redundant storage systems' [patent_app_type] => 1 [patent_app_number] => 9/001298 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12095 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233696.pdf [firstpage_image] =>[orig_patent_app_number] => 001298 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001298
Data verification and repair in redundant storage systems Dec 30, 1997 Issued
Array ( [id] => 4088479 [patent_doc_number] => 06070213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Telecommunications terminal' [patent_app_type] => 1 [patent_app_number] => 9/000998 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4778 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070213.pdf [firstpage_image] =>[orig_patent_app_number] => 000998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000998
Telecommunications terminal Dec 29, 1997 Issued
Array ( [id] => 4310852 [patent_doc_number] => 06212649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'System and method for providing highly-reliable coordination of intelligent agents in a distributed computing system' [patent_app_type] => 1 [patent_app_number] => 9/001119 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212649.pdf [firstpage_image] =>[orig_patent_app_number] => 001119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001119
System and method for providing highly-reliable coordination of intelligent agents in a distributed computing system Dec 29, 1997 Issued
Array ( [id] => 4317688 [patent_doc_number] => 06182181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Computer system with interface and method' [patent_app_type] => 1 [patent_app_number] => 8/999178 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5155 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182181.pdf [firstpage_image] =>[orig_patent_app_number] => 999178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999178
Computer system with interface and method Dec 28, 1997 Issued
Array ( [id] => 4114951 [patent_doc_number] => 06049882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Apparatus and method for reducing power consumption in a self-timed system' [patent_app_type] => 1 [patent_app_number] => 8/997329 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3393 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049882.pdf [firstpage_image] =>[orig_patent_app_number] => 997329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997329
Apparatus and method for reducing power consumption in a self-timed system Dec 22, 1997 Issued
Array ( [id] => 4316166 [patent_doc_number] => 06199131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Computer system employing optimized delayed transaction arbitration technique' [patent_app_type] => 1 [patent_app_number] => 8/995699 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 13917 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199131.pdf [firstpage_image] =>[orig_patent_app_number] => 995699 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995699
Computer system employing optimized delayed transaction arbitration technique Dec 21, 1997 Issued
Array ( [id] => 4374427 [patent_doc_number] => 06202177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Error information reporting system for an error monitoring system' [patent_app_type] => 1 [patent_app_number] => 8/995164 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1150 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202177.pdf [firstpage_image] =>[orig_patent_app_number] => 995164 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995164
Error information reporting system for an error monitoring system Dec 18, 1997 Issued
Array ( [id] => 3915898 [patent_doc_number] => 05951660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Current control interface arrangement' [patent_app_type] => 1 [patent_app_number] => 8/987949 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951660.pdf [firstpage_image] =>[orig_patent_app_number] => 987949 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987949
Current control interface arrangement Dec 9, 1997 Issued
Array ( [id] => 3918634 [patent_doc_number] => 05898846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'CPU interconnect system for a computer' [patent_app_type] => 1 [patent_app_number] => 8/986858 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2981 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898846.pdf [firstpage_image] =>[orig_patent_app_number] => 986858 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986858
CPU interconnect system for a computer Dec 7, 1997 Issued
Array ( [id] => 4236148 [patent_doc_number] => 06041370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'FIFO using a fading ones counter' [patent_app_type] => 1 [patent_app_number] => 8/986502 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4615 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041370.pdf [firstpage_image] =>[orig_patent_app_number] => 986502 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986502
FIFO using a fading ones counter Dec 7, 1997 Issued
Menu