
David Armand Wiley
Director (ID: 6423, Phone: (571)272-4150 , Office: P/2100 )
| Most Active Art Unit | 2781 |
| Art Unit(s) | 2100, 2855, 2143, 2155, 2174, 2305, 2158, 2781, 3781 |
| Total Applications | 523 |
| Issued Applications | 399 |
| Pending Applications | 75 |
| Abandoned Applications | 54 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3951601
[patent_doc_number] => 05872935
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Method and apparatus for providing a remotely located outrigger card electrically coupled to a control card'
[patent_app_type] => 1
[patent_app_number] => 8/796003
[patent_app_country] => US
[patent_app_date] => 1997-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/872/05872935.pdf
[firstpage_image] =>[orig_patent_app_number] => 796003
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/796003 | Method and apparatus for providing a remotely located outrigger card electrically coupled to a control card | Feb 4, 1997 | Issued |
Array
(
[id] => 3803524
[patent_doc_number] => 05781187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system'
[patent_app_type] => 1
[patent_app_number] => 8/794526
[patent_app_country] => US
[patent_app_date] => 1997-02-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/794526 | Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system | Feb 2, 1997 | Issued |
Array
(
[id] => 3915401
[patent_doc_number] => 05944808
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Partial parity correction logic'
[patent_app_type] => 1
[patent_app_number] => 8/792892
[patent_app_country] => US
[patent_app_date] => 1997-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/792892 | Partial parity correction logic | Jan 30, 1997 | Issued |
| 08/791004 | PCI TO ISA INTERRUPT PROTOCOL CONVERTER AND SELECTION MECHANISM | Jan 26, 1997 | Abandoned |
Array
(
[id] => 3829938
[patent_doc_number] => 05812802
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Bus system with a reduced number of lines'
[patent_app_type] => 1
[patent_app_number] => 8/786348
[patent_app_country] => US
[patent_app_date] => 1997-01-23
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[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/786348 | Bus system with a reduced number of lines | Jan 22, 1997 | Issued |
Array
(
[id] => 4057275
[patent_doc_number] => 05909583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Method for making redundant power supplies hot-pluggable'
[patent_app_type] => 1
[patent_app_number] => 8/785490
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[patent_app_date] => 1997-01-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/785490 | Method for making redundant power supplies hot-pluggable | Jan 16, 1997 | Issued |
Array
(
[id] => 3794039
[patent_doc_number] => 05809259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/777273
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[firstpage_image] =>[orig_patent_app_number] => 777273
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777273 | Semiconductor integrated circuit device | Jan 5, 1997 | Issued |
Array
(
[id] => 3784474
[patent_doc_number] => 05734854
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-31
[patent_title] => 'Fast instruction decoding in a pipeline processor'
[patent_app_type] => 1
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[patent_app_country] => US
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[pdf_file] => patents/05/734/05734854.pdf
[firstpage_image] =>[orig_patent_app_number] => 778614
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778614 | Fast instruction decoding in a pipeline processor | Jan 5, 1997 | Issued |
Array
(
[id] => 3794025
[patent_doc_number] => 05809258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Bus with high gross data transfer rate'
[patent_app_type] => 1
[patent_app_number] => 8/778785
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
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[pdf_file] => patents/05/809/05809258.pdf
[firstpage_image] =>[orig_patent_app_number] => 778785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778785 | Bus with high gross data transfer rate | Jan 5, 1997 | Issued |
Array
(
[id] => 3916012
[patent_doc_number] => 05951667
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Method and apparatus for connecting expansion buses to a peripheral component interconnect bus'
[patent_app_type] => 1
[patent_app_number] => 8/778192
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[patent_app_date] => 1997-01-02
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[pdf_file] => patents/05/951/05951667.pdf
[firstpage_image] =>[orig_patent_app_number] => 778192
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778192 | Method and apparatus for connecting expansion buses to a peripheral component interconnect bus | Jan 1, 1997 | Issued |
Array
(
[id] => 3993230
[patent_doc_number] => 05918060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Monitor power supply adjusting circuit for computer system'
[patent_app_type] => 1
[patent_app_number] => 8/778092
[patent_app_country] => US
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[pdf_file] => patents/05/918/05918060.pdf
[firstpage_image] =>[orig_patent_app_number] => 778092
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778092 | Monitor power supply adjusting circuit for computer system | Jan 1, 1997 | Issued |
Array
(
[id] => 4067993
[patent_doc_number] => 05933614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Isolation of PCI and EISA masters by masking control and interrupt lines'
[patent_app_type] => 1
[patent_app_number] => 8/775392
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[patent_app_date] => 1996-12-31
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[pdf_file] => patents/05/933/05933614.pdf
[firstpage_image] =>[orig_patent_app_number] => 775392
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/775392 | Isolation of PCI and EISA masters by masking control and interrupt lines | Dec 30, 1996 | Issued |
Array
(
[id] => 3888311
[patent_doc_number] => 05838982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Power switch method and apparatus for preventing a failure in the power controller'
[patent_app_type] => 1
[patent_app_number] => 8/769386
[patent_app_country] => US
[patent_app_date] => 1996-12-19
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[pdf_file] => patents/05/838/05838982.pdf
[firstpage_image] =>[orig_patent_app_number] => 769386
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/769386 | Power switch method and apparatus for preventing a failure in the power controller | Dec 18, 1996 | Issued |
Array
(
[id] => 3813678
[patent_doc_number] => 05828891
[patent_country] => US
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[patent_title] => 'Multilevel interrupt device'
[patent_app_type] => 1
[patent_app_number] => 8/766689
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[pdf_file] => patents/05/828/05828891.pdf
[firstpage_image] =>[orig_patent_app_number] => 766689
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/766689 | Multilevel interrupt device | Dec 12, 1996 | Issued |
Array
(
[id] => 3700008
[patent_doc_number] => 05696911
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[patent_issue_date] => 1997-12-09
[patent_title] => 'Arrangement for eliminating malfunction and/or permitting high-speed transmission in a serial bus connection, and transmitter and receiver units linked to the latter'
[patent_app_type] => 1
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[pdf_file] => patents/05/696/05696911.pdf
[firstpage_image] =>[orig_patent_app_number] => 763349
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763349 | Arrangement for eliminating malfunction and/or permitting high-speed transmission in a serial bus connection, and transmitter and receiver units linked to the latter | Dec 10, 1996 | Issued |
Array
(
[id] => 4239556
[patent_doc_number] => 06088807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Computer system with low power mode invoked by halt instruction'
[patent_app_type] => 1
[patent_app_number] => 8/777772
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[patent_app_date] => 1996-12-09
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[firstpage_image] =>[orig_patent_app_number] => 777772
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777772 | Computer system with low power mode invoked by halt instruction | Dec 8, 1996 | Issued |
| 08/754470 | CPU-PERIPHERAL BUS INTERFACE USING BYTE ENABLE SIGNALING TO CONTROL BYTE LANE STEERING | Nov 21, 1996 | Abandoned |
Array
(
[id] => 3670697
[patent_doc_number] => 05659759
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[patent_issue_date] => 1997-08-19
[patent_title] => 'Data processing device having improved interrupt controller to process interrupts of different priority levels'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742699 | Data processing device having improved interrupt controller to process interrupts of different priority levels | Nov 3, 1996 | Issued |
Array
(
[id] => 3766900
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[patent_title] => 'Information processing apparatus incorporating automatic SCSI ID generation'
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[firstpage_image] =>[orig_patent_app_number] => 732663
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/732663 | Information processing apparatus incorporating automatic SCSI ID generation | Oct 15, 1996 | Issued |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 724815
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/724815 | Data processing system | Oct 1, 1996 | Issued |