Search

David Armand Wiley

Director (ID: 6423, Phone: (571)272-4150 , Office: P/2100 )

Most Active Art Unit
2781
Art Unit(s)
2100, 2855, 2143, 2155, 2174, 2305, 2158, 2781, 3781
Total Applications
523
Issued Applications
399
Pending Applications
75
Abandoned Applications
54

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3951601 [patent_doc_number] => 05872935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Method and apparatus for providing a remotely located outrigger card electrically coupled to a control card' [patent_app_type] => 1 [patent_app_number] => 8/796003 [patent_app_country] => US [patent_app_date] => 1997-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4259 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872935.pdf [firstpage_image] =>[orig_patent_app_number] => 796003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/796003
Method and apparatus for providing a remotely located outrigger card electrically coupled to a control card Feb 4, 1997 Issued
Array ( [id] => 3803524 [patent_doc_number] => 05781187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system' [patent_app_type] => 1 [patent_app_number] => 8/794526 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 12428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781187.pdf [firstpage_image] =>[orig_patent_app_number] => 794526 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794526
Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system Feb 2, 1997 Issued
Array ( [id] => 3915401 [patent_doc_number] => 05944808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Partial parity correction logic' [patent_app_type] => 1 [patent_app_number] => 8/792892 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 9222 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944808.pdf [firstpage_image] =>[orig_patent_app_number] => 792892 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792892
Partial parity correction logic Jan 30, 1997 Issued
08/791004 PCI TO ISA INTERRUPT PROTOCOL CONVERTER AND SELECTION MECHANISM Jan 26, 1997 Abandoned
Array ( [id] => 3829938 [patent_doc_number] => 05812802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Bus system with a reduced number of lines' [patent_app_type] => 1 [patent_app_number] => 8/786348 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3680 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812802.pdf [firstpage_image] =>[orig_patent_app_number] => 786348 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786348
Bus system with a reduced number of lines Jan 22, 1997 Issued
Array ( [id] => 4057275 [patent_doc_number] => 05909583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Method for making redundant power supplies hot-pluggable' [patent_app_type] => 1 [patent_app_number] => 8/785490 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3666 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909583.pdf [firstpage_image] =>[orig_patent_app_number] => 785490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785490
Method for making redundant power supplies hot-pluggable Jan 16, 1997 Issued
Array ( [id] => 3794039 [patent_doc_number] => 05809259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/777273 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 21691 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809259.pdf [firstpage_image] =>[orig_patent_app_number] => 777273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777273
Semiconductor integrated circuit device Jan 5, 1997 Issued
Array ( [id] => 3784474 [patent_doc_number] => 05734854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Fast instruction decoding in a pipeline processor' [patent_app_type] => 1 [patent_app_number] => 8/778614 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4576 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734854.pdf [firstpage_image] =>[orig_patent_app_number] => 778614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778614
Fast instruction decoding in a pipeline processor Jan 5, 1997 Issued
Array ( [id] => 3794025 [patent_doc_number] => 05809258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Bus with high gross data transfer rate' [patent_app_type] => 1 [patent_app_number] => 8/778785 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 20512 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809258.pdf [firstpage_image] =>[orig_patent_app_number] => 778785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778785
Bus with high gross data transfer rate Jan 5, 1997 Issued
Array ( [id] => 3916012 [patent_doc_number] => 05951667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and apparatus for connecting expansion buses to a peripheral component interconnect bus' [patent_app_type] => 1 [patent_app_number] => 8/778192 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5192 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951667.pdf [firstpage_image] =>[orig_patent_app_number] => 778192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778192
Method and apparatus for connecting expansion buses to a peripheral component interconnect bus Jan 1, 1997 Issued
Array ( [id] => 3993230 [patent_doc_number] => 05918060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Monitor power supply adjusting circuit for computer system' [patent_app_type] => 1 [patent_app_number] => 8/778092 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2114 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918060.pdf [firstpage_image] =>[orig_patent_app_number] => 778092 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778092
Monitor power supply adjusting circuit for computer system Jan 1, 1997 Issued
Array ( [id] => 4067993 [patent_doc_number] => 05933614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Isolation of PCI and EISA masters by masking control and interrupt lines' [patent_app_type] => 1 [patent_app_number] => 8/775392 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 18259 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933614.pdf [firstpage_image] =>[orig_patent_app_number] => 775392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775392
Isolation of PCI and EISA masters by masking control and interrupt lines Dec 30, 1996 Issued
Array ( [id] => 3888311 [patent_doc_number] => 05838982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Power switch method and apparatus for preventing a failure in the power controller' [patent_app_type] => 1 [patent_app_number] => 8/769386 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2101 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838982.pdf [firstpage_image] =>[orig_patent_app_number] => 769386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769386
Power switch method and apparatus for preventing a failure in the power controller Dec 18, 1996 Issued
Array ( [id] => 3813678 [patent_doc_number] => 05828891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Multilevel interrupt device' [patent_app_type] => 1 [patent_app_number] => 8/766689 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4011 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828891.pdf [firstpage_image] =>[orig_patent_app_number] => 766689 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766689
Multilevel interrupt device Dec 12, 1996 Issued
Array ( [id] => 3700008 [patent_doc_number] => 05696911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Arrangement for eliminating malfunction and/or permitting high-speed transmission in a serial bus connection, and transmitter and receiver units linked to the latter' [patent_app_type] => 1 [patent_app_number] => 8/763349 [patent_app_country] => US [patent_app_date] => 1996-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4244 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696911.pdf [firstpage_image] =>[orig_patent_app_number] => 763349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763349
Arrangement for eliminating malfunction and/or permitting high-speed transmission in a serial bus connection, and transmitter and receiver units linked to the latter Dec 10, 1996 Issued
Array ( [id] => 4239556 [patent_doc_number] => 06088807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Computer system with low power mode invoked by halt instruction' [patent_app_type] => 1 [patent_app_number] => 8/777772 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3528 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088807.pdf [firstpage_image] =>[orig_patent_app_number] => 777772 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777772
Computer system with low power mode invoked by halt instruction Dec 8, 1996 Issued
08/754470 CPU-PERIPHERAL BUS INTERFACE USING BYTE ENABLE SIGNALING TO CONTROL BYTE LANE STEERING Nov 21, 1996 Abandoned
Array ( [id] => 3670697 [patent_doc_number] => 05659759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Data processing device having improved interrupt controller to process interrupts of different priority levels' [patent_app_type] => 1 [patent_app_number] => 8/742699 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5432 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659759.pdf [firstpage_image] =>[orig_patent_app_number] => 742699 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/742699
Data processing device having improved interrupt controller to process interrupts of different priority levels Nov 3, 1996 Issued
Array ( [id] => 3766900 [patent_doc_number] => 05721840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Information processing apparatus incorporating automatic SCSI ID generation' [patent_app_type] => 1 [patent_app_number] => 8/732663 [patent_app_country] => US [patent_app_date] => 1996-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6063 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721840.pdf [firstpage_image] =>[orig_patent_app_number] => 732663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/732663
Information processing apparatus incorporating automatic SCSI ID generation Oct 15, 1996 Issued
Array ( [id] => 3634062 [patent_doc_number] => 05689658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Data processing system' [patent_app_type] => 1 [patent_app_number] => 8/724815 [patent_app_country] => US [patent_app_date] => 1996-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8199 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689658.pdf [firstpage_image] =>[orig_patent_app_number] => 724815 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724815
Data processing system Oct 1, 1996 Issued
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