Search

David Armand Wiley

Examiner (ID: 5040)

Most Active Art Unit
2781
Art Unit(s)
2174, 2158, 2305, 2100, 2155, 3781, 2781, 2143, 2855
Total Applications
522
Issued Applications
399
Pending Applications
75
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
08/683801 INTERRUPT TRANSMISSION VIA SPECIALIZED BUS CYCLE WITHIN A SYMMETRICAL MULTIPROCESSING SYSTEM Jul 17, 1996 Abandoned
Array ( [id] => 3971471 [patent_doc_number] => 06000036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Logical steering to avoid hot spots on integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/682472 [patent_app_country] => US [patent_app_date] => 1996-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000036.pdf [firstpage_image] =>[orig_patent_app_number] => 682472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/682472
Logical steering to avoid hot spots on integrated circuits Jul 16, 1996 Issued
Array ( [id] => 3897165 [patent_doc_number] => 05805835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Parallel architecture computer system and method' [patent_app_type] => 1 [patent_app_number] => 8/679834 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3381 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805835.pdf [firstpage_image] =>[orig_patent_app_number] => 679834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679834
Parallel architecture computer system and method Jul 14, 1996 Issued
Array ( [id] => 3997028 [patent_doc_number] => 05961618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Dual-bus riser card for an expansion slot' [patent_app_type] => 1 [patent_app_number] => 8/679432 [patent_app_country] => US [patent_app_date] => 1996-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3700 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961618.pdf [firstpage_image] =>[orig_patent_app_number] => 679432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679432
Dual-bus riser card for an expansion slot Jul 7, 1996 Issued
Array ( [id] => 3898232 [patent_doc_number] => 05805904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Power control circuit of at least one computer expansion slot' [patent_app_type] => 1 [patent_app_number] => 8/677369 [patent_app_country] => US [patent_app_date] => 1996-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1719 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805904.pdf [firstpage_image] =>[orig_patent_app_number] => 677369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677369
Power control circuit of at least one computer expansion slot Jul 4, 1996 Issued
Array ( [id] => 3961316 [patent_doc_number] => 05974493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Microcomputer with processor bus having smaller width than memory bus' [patent_app_type] => 1 [patent_app_number] => 8/674873 [patent_app_country] => US [patent_app_date] => 1996-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 12641 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974493.pdf [firstpage_image] =>[orig_patent_app_number] => 674873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674873
Microcomputer with processor bus having smaller width than memory bus Jul 1, 1996 Issued
Array ( [id] => 3997998 [patent_doc_number] => 05862357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Hierarchical SMP computer system' [patent_app_type] => 1 [patent_app_number] => 8/674688 [patent_app_country] => US [patent_app_date] => 1996-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4404 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862357.pdf [firstpage_image] =>[orig_patent_app_number] => 674688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674688
Hierarchical SMP computer system Jul 1, 1996 Issued
Array ( [id] => 3973188 [patent_doc_number] => 05978874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Implementing snooping on a split-transaction computer system bus' [patent_app_type] => 1 [patent_app_number] => 8/673038 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 20115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978874.pdf [firstpage_image] =>[orig_patent_app_number] => 673038 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673038
Implementing snooping on a split-transaction computer system bus Jun 30, 1996 Issued
Array ( [id] => 4021643 [patent_doc_number] => 05987549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and apparatus providing short latency round-robin arbitration for access to a shared resource' [patent_app_type] => 1 [patent_app_number] => 8/675286 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 23011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987549.pdf [firstpage_image] =>[orig_patent_app_number] => 675286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675286
Method and apparatus providing short latency round-robin arbitration for access to a shared resource Jun 30, 1996 Issued
Array ( [id] => 3995860 [patent_doc_number] => 05911052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Split transaction snooping bus protocol' [patent_app_type] => 1 [patent_app_number] => 8/673967 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 20148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911052.pdf [firstpage_image] =>[orig_patent_app_number] => 673967 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673967
Split transaction snooping bus protocol Jun 30, 1996 Issued
Array ( [id] => 4031066 [patent_doc_number] => 05881254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Inter-bus bridge circuit with integrated memory port' [patent_app_type] => 1 [patent_app_number] => 8/674592 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4101 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881254.pdf [firstpage_image] =>[orig_patent_app_number] => 674592 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674592
Inter-bus bridge circuit with integrated memory port Jun 27, 1996 Issued
Array ( [id] => 4029925 [patent_doc_number] => 05907688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Smart arbitration for non-symmetric data streams' [patent_app_type] => 1 [patent_app_number] => 8/673329 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5555 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907688.pdf [firstpage_image] =>[orig_patent_app_number] => 673329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673329
Smart arbitration for non-symmetric data streams Jun 27, 1996 Issued
Array ( [id] => 3841562 [patent_doc_number] => 05784580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'System and method for communicating between devices' [patent_app_type] => 1 [patent_app_number] => 8/673394 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5722 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784580.pdf [firstpage_image] =>[orig_patent_app_number] => 673394 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673394
System and method for communicating between devices Jun 27, 1996 Issued
Array ( [id] => 3803849 [patent_doc_number] => 05737614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Dynamic control of power consumption in self-timed circuits' [patent_app_type] => 1 [patent_app_number] => 8/671189 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4076 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737614.pdf [firstpage_image] =>[orig_patent_app_number] => 671189 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671189
Dynamic control of power consumption in self-timed circuits Jun 26, 1996 Issued
Array ( [id] => 3910055 [patent_doc_number] => 05835738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Address space architecture for multiple bus computer systems' [patent_app_type] => 1 [patent_app_number] => 8/668530 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7099 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835738.pdf [firstpage_image] =>[orig_patent_app_number] => 668530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668530
Address space architecture for multiple bus computer systems Jun 23, 1996 Issued
Array ( [id] => 3894587 [patent_doc_number] => 05799160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Circuit and method for controlling bus arbitration' [patent_app_type] => 1 [patent_app_number] => 8/669071 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2532 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799160.pdf [firstpage_image] =>[orig_patent_app_number] => 669071 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/669071
Circuit and method for controlling bus arbitration Jun 23, 1996 Issued
Array ( [id] => 3761698 [patent_doc_number] => 05802323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Transparent burst access to data having a portion residing in cache and a portion residing in memory' [patent_app_type] => 1 [patent_app_number] => 8/663968 [patent_app_country] => US [patent_app_date] => 1996-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9847 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802323.pdf [firstpage_image] =>[orig_patent_app_number] => 663968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663968
Transparent burst access to data having a portion residing in cache and a portion residing in memory Jun 13, 1996 Issued
Array ( [id] => 3837424 [patent_doc_number] => 05790893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Segmented concurrent receive/transfer interface using shared RAM storage' [patent_app_type] => 1 [patent_app_number] => 8/658791 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2563 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790893.pdf [firstpage_image] =>[orig_patent_app_number] => 658791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658791
Segmented concurrent receive/transfer interface using shared RAM storage Jun 4, 1996 Issued
Array ( [id] => 3951657 [patent_doc_number] => 05872939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Bus arbitration' [patent_app_type] => 1 [patent_app_number] => 8/658485 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 127 [patent_figures_cnt] => 146 [patent_no_of_words] => 71843 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872939.pdf [firstpage_image] =>[orig_patent_app_number] => 658485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658485
Bus arbitration Jun 4, 1996 Issued
Array ( [id] => 3872155 [patent_doc_number] => 05768546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Method and apparatus for bi-directional transfer of data between two buses with different widths' [patent_app_type] => 1 [patent_app_number] => 8/658424 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3198 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768546.pdf [firstpage_image] =>[orig_patent_app_number] => 658424 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658424
Method and apparatus for bi-directional transfer of data between two buses with different widths Jun 4, 1996 Issued
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