Search

David Armand Wiley

Director (ID: 6423, Phone: (571)272-4150 , Office: P/2100 )

Most Active Art Unit
2781
Art Unit(s)
2100, 2855, 2143, 2155, 2174, 2305, 2158, 2781, 3781
Total Applications
523
Issued Applications
399
Pending Applications
75
Abandoned Applications
54

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3829854 [patent_doc_number] => 05812798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Data processing system for accessing an external device and method therefore' [patent_app_type] => 1 [patent_app_number] => 8/592271 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8443 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812798.pdf [firstpage_image] =>[orig_patent_app_number] => 592271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592271
Data processing system for accessing an external device and method therefore Jan 25, 1996 Issued
Array ( [id] => 3842272 [patent_doc_number] => 05784627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Integrated timer for power management and watchdog functions' [patent_app_type] => 1 [patent_app_number] => 8/590967 [patent_app_country] => US [patent_app_date] => 1996-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3503 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784627.pdf [firstpage_image] =>[orig_patent_app_number] => 590967 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590967
Integrated timer for power management and watchdog functions Jan 23, 1996 Issued
Array ( [id] => 3870715 [patent_doc_number] => 05706444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method and apparatus for transmission of signals over a shared line' [patent_app_type] => 1 [patent_app_number] => 8/590954 [patent_app_country] => US [patent_app_date] => 1996-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8651 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706444.pdf [firstpage_image] =>[orig_patent_app_number] => 590954 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590954
Method and apparatus for transmission of signals over a shared line Jan 23, 1996 Issued
Array ( [id] => 3708965 [patent_doc_number] => 05619697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Inter-processor communication system for performing message communication between processors and multi-processor real time system for communicating amoung a plurality of processors at real time with the inter-processor communication system' [patent_app_type] => 1 [patent_app_number] => 8/589415 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10789 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619697.pdf [firstpage_image] =>[orig_patent_app_number] => 589415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/589415
Inter-processor communication system for performing message communication between processors and multi-processor real time system for communicating amoung a plurality of processors at real time with the inter-processor communication system Jan 21, 1996 Issued
Array ( [id] => 3878475 [patent_doc_number] => 05793997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Interface architecture for connection to a peripheral component interconnect bus' [patent_app_type] => 1 [patent_app_number] => 8/584413 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4481 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793997.pdf [firstpage_image] =>[orig_patent_app_number] => 584413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/584413
Interface architecture for connection to a peripheral component interconnect bus Jan 10, 1996 Issued
Array ( [id] => 3637126 [patent_doc_number] => 05603040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Power management control unit for a computer peripheral' [patent_app_type] => 1 [patent_app_number] => 8/581750 [patent_app_country] => US [patent_app_date] => 1996-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4164 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603040.pdf [firstpage_image] =>[orig_patent_app_number] => 581750 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581750
Power management control unit for a computer peripheral Jan 1, 1996 Issued
Array ( [id] => 3796472 [patent_doc_number] => 05819051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Low speed serial bus protocol and circuitry' [patent_app_type] => 1 [patent_app_number] => 8/578168 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819051.pdf [firstpage_image] =>[orig_patent_app_number] => 578168 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/578168
Low speed serial bus protocol and circuitry Dec 28, 1995 Issued
Array ( [id] => 3802499 [patent_doc_number] => 05822552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method and circuit for rearranging output data in variable-length decoder' [patent_app_type] => 1 [patent_app_number] => 8/581374 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 38 [patent_no_of_words] => 4632 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822552.pdf [firstpage_image] =>[orig_patent_app_number] => 581374 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581374
Method and circuit for rearranging output data in variable-length decoder Dec 28, 1995 Issued
Array ( [id] => 3848934 [patent_doc_number] => 05740454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Circuit for setting computer system bus signals to predetermined states in low power mode' [patent_app_type] => 1 [patent_app_number] => 8/576193 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15640 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740454.pdf [firstpage_image] =>[orig_patent_app_number] => 576193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/576193
Circuit for setting computer system bus signals to predetermined states in low power mode Dec 19, 1995 Issued
Array ( [id] => 3736874 [patent_doc_number] => 05701495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Scalable system interrupt structure for a multi-processing system' [patent_app_type] => 1 [patent_app_number] => 8/573918 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10025 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701495.pdf [firstpage_image] =>[orig_patent_app_number] => 573918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573918
Scalable system interrupt structure for a multi-processing system Dec 17, 1995 Issued
Array ( [id] => 3898379 [patent_doc_number] => 05748925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Dynamic realtime routing in a data communications network' [patent_app_type] => 1 [patent_app_number] => 8/573586 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1541 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748925.pdf [firstpage_image] =>[orig_patent_app_number] => 573586 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573586
Dynamic realtime routing in a data communications network Dec 14, 1995 Issued
Array ( [id] => 1409844 [patent_doc_number] => 06557106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Power enabling mechanism, a power enabling method, and a controller for an input/output device' [patent_app_type] => B1 [patent_app_number] => 08/571064 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9071 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557106.pdf [firstpage_image] =>[orig_patent_app_number] => 08571064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/571064
Power enabling mechanism, a power enabling method, and a controller for an input/output device Dec 11, 1995 Issued
Array ( [id] => 3898321 [patent_doc_number] => 05748921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory' [patent_app_type] => 1 [patent_app_number] => 8/570591 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 16231 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748921.pdf [firstpage_image] =>[orig_patent_app_number] => 570591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/570591
Computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory Dec 10, 1995 Issued
Array ( [id] => 3787971 [patent_doc_number] => 05774680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Interfacing direct memory access devices to a non-ISA bus' [patent_app_type] => 1 [patent_app_number] => 8/570394 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10839 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774680.pdf [firstpage_image] =>[orig_patent_app_number] => 570394 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/570394
Interfacing direct memory access devices to a non-ISA bus Dec 10, 1995 Issued
Array ( [id] => 3904679 [patent_doc_number] => 05778195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'PC card' [patent_app_type] => 1 [patent_app_number] => 8/560986 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4461 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778195.pdf [firstpage_image] =>[orig_patent_app_number] => 560986 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560986
PC card Nov 19, 1995 Issued
Array ( [id] => 3878640 [patent_doc_number] => 05797024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'PC card' [patent_app_type] => 1 [patent_app_number] => 8/558869 [patent_app_country] => US [patent_app_date] => 1995-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4343 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/797/05797024.pdf [firstpage_image] =>[orig_patent_app_number] => 558869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/558869
PC card Nov 15, 1995 Issued
Array ( [id] => 3735163 [patent_doc_number] => 05682555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Bus control apparatus' [patent_app_type] => 1 [patent_app_number] => 8/556803 [patent_app_country] => US [patent_app_date] => 1995-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 46 [patent_no_of_words] => 12073 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682555.pdf [firstpage_image] =>[orig_patent_app_number] => 556803 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/556803
Bus control apparatus Nov 1, 1995 Issued
Array ( [id] => 3898223 [patent_doc_number] => 05748914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Protocol for communication with dynamic memory' [patent_app_type] => 1 [patent_app_number] => 8/545292 [patent_app_country] => US [patent_app_date] => 1995-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 18412 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748914.pdf [firstpage_image] =>[orig_patent_app_number] => 545292 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/545292
Protocol for communication with dynamic memory Oct 18, 1995 Issued
Array ( [id] => 3826794 [patent_doc_number] => 05832281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Power control apparatus and power control method' [patent_app_type] => 1 [patent_app_number] => 8/544193 [patent_app_country] => US [patent_app_date] => 1995-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5819 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832281.pdf [firstpage_image] =>[orig_patent_app_number] => 544193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544193
Power control apparatus and power control method Oct 16, 1995 Issued
Array ( [id] => 3660748 [patent_doc_number] => 05630146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Method and apparatus for invalidating a cache while in a low power state' [patent_app_type] => 1 [patent_app_number] => 8/543523 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 14227 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630146.pdf [firstpage_image] =>[orig_patent_app_number] => 543523 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543523
Method and apparatus for invalidating a cache while in a low power state Oct 15, 1995 Issued
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