David Armand Wiley

Array ( [id] => 3974709 [patent_doc_number] => 05901329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Data processing terminal which determines a type of an external device' [patent_app_type] => 1 [patent_app_number] => 8/385169 [patent_app_country] => US [patent_app_date] => 1995-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 7121 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901329.pdf [firstpage_image] =>[orig_patent_app_number] => 385169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3847865 [patent_doc_number] => 05740385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Low load host/PCI bus bridge' [patent_app_type] => 1 [patent_app_number] => 8/358359 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4226 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740385.pdf [firstpage_image] =>[orig_patent_app_number] => 358359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3738970 [patent_doc_number] => 05652893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Switching hub intelligent power management' [patent_app_type] => 1 [patent_app_number] => 8/355056 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11194 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652893.pdf [firstpage_image] =>[orig_patent_app_number] => 355056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700767 [patent_doc_number] => 05692123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Maintenance channel for modulator, highly interconnected computer systems' [patent_app_type] => 1 [patent_app_number] => 8/350648 [patent_app_country] => US [patent_app_date] => 1994-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5816 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692123.pdf [firstpage_image] =>[orig_patent_app_number] => 350648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3547577 [patent_doc_number] => 05557758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses' [patent_app_type] => 1 [patent_app_number] => 8/351192 [patent_app_country] => US [patent_app_date] => 1994-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3566 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557758.pdf [firstpage_image] =>[orig_patent_app_number] => 351192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3894531 [patent_doc_number] => 05729767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'System and method for accessing peripheral devices on a non-functional controller' [patent_app_type] => 1 [patent_app_number] => 8/319689 [patent_app_country] => US [patent_app_date] => 1994-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6570 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729767.pdf [firstpage_image] =>[orig_patent_app_number] => 319689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3638202 [patent_doc_number] => 05608878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Dual latency status and coherency reporting for a multiprocessing system' [patent_app_type] => 1 [patent_app_number] => 8/316980 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608878.pdf [firstpage_image] =>[orig_patent_app_number] => 316980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3803821 [patent_doc_number] => 05737612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Power-on reset control circuit' [patent_app_type] => 1 [patent_app_number] => 8/316121 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7520 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737612.pdf [firstpage_image] =>[orig_patent_app_number] => 316121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601715 [patent_doc_number] => 05551043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Standby checkpoint to prevent data loss' [patent_app_type] => 1 [patent_app_number] => 8/303103 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 54 [patent_no_of_words] => 37798 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551043.pdf [firstpage_image] =>[orig_patent_app_number] => 303103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3599953 [patent_doc_number] => 05553251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Centralized management system utilizing a bus interface unit' [patent_app_type] => 1 [patent_app_number] => 8/204156 [patent_app_country] => US [patent_app_date] => 1994-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3723 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 602 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553251.pdf [firstpage_image] =>[orig_patent_app_number] => 204156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3612066 [patent_doc_number] => 05559969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method and apparatus for efficiently interfacing variable width data streams to a fixed width memory' [patent_app_type] => 1 [patent_app_number] => 8/287880 [patent_app_country] => US [patent_app_date] => 1994-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11631 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559969.pdf [firstpage_image] =>[orig_patent_app_number] => 287880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3794543 [patent_doc_number] => 05809293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'System and method for program execution tracing within an integrated processor' [patent_app_type] => 1 [patent_app_number] => 8/283128 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5532 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809293.pdf [firstpage_image] =>[orig_patent_app_number] => 283128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3612897 [patent_doc_number] => 05560022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Power management coordinator system and interface' [patent_app_type] => 1 [patent_app_number] => 8/278054 [patent_app_country] => US [patent_app_date] => 1994-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 21441 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/560/05560022.pdf [firstpage_image] =>[orig_patent_app_number] => 278054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3672472 [patent_doc_number] => 05592635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Technique for accelerating instruction decoding of instruction sets with variable length opcodes in a pipeline microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/276060 [patent_app_country] => US [patent_app_date] => 1994-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4609 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592635.pdf [firstpage_image] =>[orig_patent_app_number] => 276060 [rel_patent_id] =>[rel_patent_doc_number] =>)