Search

David Armand Wiley

Examiner (ID: 5040)

Most Active Art Unit
2781
Art Unit(s)
2174, 2158, 2305, 2100, 2155, 3781, 2781, 2143, 2855
Total Applications
522
Issued Applications
399
Pending Applications
75
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1438741 [patent_doc_number] => 06357013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Circuit for setting computer system bus signals to predetermined states in low power mode' [patent_app_type] => B1 [patent_app_number] => 09/042914 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 14739 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/357/06357013.pdf [firstpage_image] =>[orig_patent_app_number] => 09042914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042914
Circuit for setting computer system bus signals to predetermined states in low power mode Mar 16, 1998 Issued
Array ( [id] => 4316214 [patent_doc_number] => 06199134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Computer system with bridge logic that asserts a system management interrupt signal when an address is made to a trapped address and which also completes the cycle to the target address' [patent_app_type] => 1 [patent_app_number] => 9/041529 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9098 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199134.pdf [firstpage_image] =>[orig_patent_app_number] => 041529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/041529
Computer system with bridge logic that asserts a system management interrupt signal when an address is made to a trapped address and which also completes the cycle to the target address Mar 12, 1998 Issued
Array ( [id] => 4256802 [patent_doc_number] => 06081863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system' [patent_app_type] => 1 [patent_app_number] => 9/042101 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081863.pdf [firstpage_image] =>[orig_patent_app_number] => 042101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042101
Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system Mar 12, 1998 Issued
Array ( [id] => 4374205 [patent_doc_number] => 06202163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Data processing circuit with gating of clocking signals to various elements of the circuit' [patent_app_type] => 1 [patent_app_number] => 9/037829 [patent_app_country] => US [patent_app_date] => 1998-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5479 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202163.pdf [firstpage_image] =>[orig_patent_app_number] => 037829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/037829
Data processing circuit with gating of clocking signals to various elements of the circuit Mar 9, 1998 Issued
Array ( [id] => 4257445 [patent_doc_number] => 06081902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Control system and methods for power shutdown of a computer system' [patent_app_type] => 1 [patent_app_number] => 9/036778 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081902.pdf [firstpage_image] =>[orig_patent_app_number] => 036778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/036778
Control system and methods for power shutdown of a computer system Mar 8, 1998 Issued
Array ( [id] => 4292063 [patent_doc_number] => 06247087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Bus system for shadowing registers' [patent_app_type] => 1 [patent_app_number] => 9/036634 [patent_app_country] => US [patent_app_date] => 1998-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 13017 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247087.pdf [firstpage_image] =>[orig_patent_app_number] => 036634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/036634
Bus system for shadowing registers Mar 5, 1998 Issued
Array ( [id] => 4422174 [patent_doc_number] => 06272574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Device such as expansion card, access control method of the expansion card, and a memory medium storing a program capable of being read by computer' [patent_app_type] => 1 [patent_app_number] => 9/032783 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4435 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272574.pdf [firstpage_image] =>[orig_patent_app_number] => 032783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032783
Device such as expansion card, access control method of the expansion card, and a memory medium storing a program capable of being read by computer Mar 1, 1998 Issued
Array ( [id] => 4195453 [patent_doc_number] => 06085326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Apparatus and method for displaying DPMS mode status using an OSD circuit' [patent_app_type] => 1 [patent_app_number] => 9/024119 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2730 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085326.pdf [firstpage_image] =>[orig_patent_app_number] => 024119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024119
Apparatus and method for displaying DPMS mode status using an OSD circuit Feb 16, 1998 Issued
Array ( [id] => 4412102 [patent_doc_number] => 06298405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Data communication system, printing system and data communication apparatus' [patent_app_type] => 1 [patent_app_number] => 9/024187 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 18438 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298405.pdf [firstpage_image] =>[orig_patent_app_number] => 024187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024187
Data communication system, printing system and data communication apparatus Feb 16, 1998 Issued
Array ( [id] => 3996360 [patent_doc_number] => 05911084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'System and method for accessing peripheral devices on a non-functional controller' [patent_app_type] => 1 [patent_app_number] => 9/024719 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6570 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911084.pdf [firstpage_image] =>[orig_patent_app_number] => 024719 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024719
System and method for accessing peripheral devices on a non-functional controller Feb 16, 1998 Issued
Array ( [id] => 4238722 [patent_doc_number] => 06088751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Highly configurable bus priority arbitration system' [patent_app_type] => 1 [patent_app_number] => 9/023053 [patent_app_country] => US [patent_app_date] => 1998-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 11 [patent_no_of_words] => 9875 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088751.pdf [firstpage_image] =>[orig_patent_app_number] => 023053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023053
Highly configurable bus priority arbitration system Feb 11, 1998 Issued
Array ( [id] => 4177662 [patent_doc_number] => 06105140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Secure power supply' [patent_app_type] => 1 [patent_app_number] => 9/021185 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6905 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105140.pdf [firstpage_image] =>[orig_patent_app_number] => 021185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021185
Secure power supply Feb 9, 1998 Issued
Array ( [id] => 3915697 [patent_doc_number] => 05944827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Power saving control system and method for use with serially connected electronic devices' [patent_app_type] => 1 [patent_app_number] => 9/038474 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5825 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944827.pdf [firstpage_image] =>[orig_patent_app_number] => 038474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038474
Power saving control system and method for use with serially connected electronic devices Feb 1, 1998 Issued
Array ( [id] => 4259998 [patent_doc_number] => 06167474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Apparatus and method for distributed arbitration of shared resources' [patent_app_type] => 1 [patent_app_number] => 9/015587 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5378 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167474.pdf [firstpage_image] =>[orig_patent_app_number] => 015587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015587
Apparatus and method for distributed arbitration of shared resources Jan 28, 1998 Issued
Array ( [id] => 4280283 [patent_doc_number] => 06205551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Computer security using virus probing' [patent_app_type] => 1 [patent_app_number] => 9/015563 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4859 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205551.pdf [firstpage_image] =>[orig_patent_app_number] => 015563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015563
Computer security using virus probing Jan 28, 1998 Issued
Array ( [id] => 4426958 [patent_doc_number] => 06195757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method for supporting 11/2 cycle data paths via PLL based clock system' [patent_app_type] => 1 [patent_app_number] => 9/013637 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3108 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195757.pdf [firstpage_image] =>[orig_patent_app_number] => 013637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013637
Method for supporting 11/2 cycle data paths via PLL based clock system Jan 25, 1998 Issued
Array ( [id] => 4318446 [patent_doc_number] => 06185702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method and system for process state management using checkpoints' [patent_app_type] => 1 [patent_app_number] => 9/012463 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5912 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185702.pdf [firstpage_image] =>[orig_patent_app_number] => 012463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012463
Method and system for process state management using checkpoints Jan 22, 1998 Issued
Array ( [id] => 4110556 [patent_doc_number] => 06134665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Computer with remote wake up and transmission of a status packet when the computer fails a self test' [patent_app_type] => 1 [patent_app_number] => 9/009809 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 42 [patent_no_of_words] => 20927 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134665.pdf [firstpage_image] =>[orig_patent_app_number] => 009809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009809
Computer with remote wake up and transmission of a status packet when the computer fails a self test Jan 19, 1998 Issued
Array ( [id] => 4179694 [patent_doc_number] => 06115824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Apparatus and a method for avoiding the accidental termination of computer power' [patent_app_type] => 1 [patent_app_number] => 9/009742 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3228 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115824.pdf [firstpage_image] =>[orig_patent_app_number] => 009742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009742
Apparatus and a method for avoiding the accidental termination of computer power Jan 19, 1998 Issued
Array ( [id] => 4260674 [patent_doc_number] => 06092209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method and apparatus for managing power consumption of peripheral devices of personal computers' [patent_app_type] => 1 [patent_app_number] => 9/008755 [patent_app_country] => US [patent_app_date] => 1998-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4249 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092209.pdf [firstpage_image] =>[orig_patent_app_number] => 008755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008755
Method and apparatus for managing power consumption of peripheral devices of personal computers Jan 18, 1998 Issued
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