| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4209847
[patent_doc_number] => 06078075
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Semiconductor device with a programmable element having a P-type substrate and floating gate with a thin gate dielectric'
[patent_app_type] => 1
[patent_app_number] => 9/028430
[patent_app_country] => US
[patent_app_date] => 1998-02-24
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[pdf_file] => patents/06/078/06078075.pdf
[firstpage_image] =>[orig_patent_app_number] => 028430
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/028430 | Semiconductor device with a programmable element having a P-type substrate and floating gate with a thin gate dielectric | Feb 23, 1998 | Issued |
Array
(
[id] => 3940380
[patent_doc_number] => 05929495
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Semiconductor processing method of forming a static random access memory cell and static random access memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/028300
[patent_app_country] => US
[patent_app_date] => 1998-02-24
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[pdf_file] => patents/05/929/05929495.pdf
[firstpage_image] =>[orig_patent_app_number] => 028300
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/028300 | Semiconductor processing method of forming a static random access memory cell and static random access memory cell | Feb 23, 1998 | Issued |
Array
(
[id] => 4227838
[patent_doc_number] => 06011305
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Semiconductor device having metal alloy for electrodes'
[patent_app_type] => 1
[patent_app_number] => 9/027953
[patent_app_country] => US
[patent_app_date] => 1998-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/06/011/06011305.pdf
[firstpage_image] =>[orig_patent_app_number] => 027953
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/027953 | Semiconductor device having metal alloy for electrodes | Feb 22, 1998 | Issued |
Array
(
[id] => 3980614
[patent_doc_number] => 05917222
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Intergrated circuit combining high frequency bipolar and high power CMOS transistors'
[patent_app_type] => 1
[patent_app_number] => 9/027160
[patent_app_country] => US
[patent_app_date] => 1998-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 5789
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/917/05917222.pdf
[firstpage_image] =>[orig_patent_app_number] => 027160
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/027160 | Intergrated circuit combining high frequency bipolar and high power CMOS transistors | Feb 19, 1998 | Issued |
Array
(
[id] => 4009428
[patent_doc_number] => 06005269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'DRAM cell with a double-crown shaped capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/025970
[patent_app_country] => US
[patent_app_date] => 1998-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/005/06005269.pdf
[firstpage_image] =>[orig_patent_app_number] => 025970
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/025970 | DRAM cell with a double-crown shaped capacitor | Feb 18, 1998 | Issued |
Array
(
[id] => 4089391
[patent_doc_number] => 06163044
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Method and circuit for lowering standby current in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/027111
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[patent_app_date] => 1998-02-18
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[pdf_file] => patents/06/163/06163044.pdf
[firstpage_image] =>[orig_patent_app_number] => 027111
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/027111 | Method and circuit for lowering standby current in an integrated circuit | Feb 17, 1998 | Issued |
Array
(
[id] => 4137099
[patent_doc_number] => 06034409
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Isolation trench having plural profile angles'
[patent_app_type] => 1
[patent_app_number] => 9/024312
[patent_app_country] => US
[patent_app_date] => 1998-02-17
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[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/034/06034409.pdf
[firstpage_image] =>[orig_patent_app_number] => 024312
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024312 | Isolation trench having plural profile angles | Feb 16, 1998 | Issued |
Array
(
[id] => 4027136
[patent_doc_number] => 05925921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Geometrical layout technique for a circular capacitor within an array of matched capacitors on a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/023882
[patent_app_country] => US
[patent_app_date] => 1998-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/925/05925921.pdf
[firstpage_image] =>[orig_patent_app_number] => 023882
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/023882 | Geometrical layout technique for a circular capacitor within an array of matched capacitors on a semiconductor device | Feb 12, 1998 | Issued |
Array
(
[id] => 4244197
[patent_doc_number] => 06081032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Dual damascene multi-level metallization and interconnection structure'
[patent_app_type] => 1
[patent_app_number] => 9/023260
[patent_app_country] => US
[patent_app_date] => 1998-02-13
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[pdf_file] => patents/06/081/06081032.pdf
[firstpage_image] =>[orig_patent_app_number] => 023260
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/023260 | Dual damascene multi-level metallization and interconnection structure | Feb 12, 1998 | Issued |
Array
(
[id] => 3929449
[patent_doc_number] => 05945718
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Self-aligned metal-oxide-compound semiconductor device and method of fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/022593
[patent_app_country] => US
[patent_app_date] => 1998-02-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/945/05945718.pdf
[firstpage_image] =>[orig_patent_app_number] => 022593
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/022593 | Self-aligned metal-oxide-compound semiconductor device and method of fabrication | Feb 11, 1998 | Issued |
| 09/022450 | ELECTRON TUBE HAVING A SEMICONDUCTOR CATHODE WITH LOWER AND HIGHER BANDGAP LAYERS | Feb 11, 1998 | Issued |
Array
(
[id] => 4070599
[patent_doc_number] => 06008526
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Device isolation layer for a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/022149
[patent_app_country] => US
[patent_app_date] => 1998-02-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/008/06008526.pdf
[firstpage_image] =>[orig_patent_app_number] => 022149
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/022149 | Device isolation layer for a semiconductor device | Feb 10, 1998 | Issued |
Array
(
[id] => 4075854
[patent_doc_number] => 06069382
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Non-volatile memory cell having a high coupling ratio'
[patent_app_type] => 1
[patent_app_number] => 9/022222
[patent_app_country] => US
[patent_app_date] => 1998-02-11
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[firstpage_image] =>[orig_patent_app_number] => 022222
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/022222 | Non-volatile memory cell having a high coupling ratio | Feb 10, 1998 | Issued |
| 09/018871 | CORELESS PCB-BASED TRANSFORMERS | Feb 4, 1998 | Abandoned |
Array
(
[id] => 4239272
[patent_doc_number] => 06118163
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Transistor with integrated poly/metal gate electrode'
[patent_app_type] => 1
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[patent_app_date] => 1998-02-04
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[firstpage_image] =>[orig_patent_app_number] => 017720
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017720 | Transistor with integrated poly/metal gate electrode | Feb 3, 1998 | Issued |
Array
(
[id] => 4183793
[patent_doc_number] => 06037617
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[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'SOI IGFETs having raised integration level'
[patent_app_type] => 1
[patent_app_number] => 9/018052
[patent_app_country] => US
[patent_app_date] => 1998-02-03
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[pdf_file] => patents/06/037/06037617.pdf
[firstpage_image] =>[orig_patent_app_number] => 018052
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/018052 | SOI IGFETs having raised integration level | Feb 2, 1998 | Issued |
Array
(
[id] => 4021938
[patent_doc_number] => 05907161
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'Semiconductor device including doped spontaneously formed superlattice layer'
[patent_app_type] => 1
[patent_app_number] => 9/017422
[patent_app_country] => US
[patent_app_date] => 1998-02-02
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[firstpage_image] =>[orig_patent_app_number] => 017422
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017422 | Semiconductor device including doped spontaneously formed superlattice layer | Feb 1, 1998 | Issued |
Array
(
[id] => 3954856
[patent_doc_number] => 05955785
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Copper-containing plug for connection of semiconductor surface with overlying conductor'
[patent_app_type] => 1
[patent_app_number] => 9/013762
[patent_app_country] => US
[patent_app_date] => 1998-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[firstpage_image] =>[orig_patent_app_number] => 013762
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/013762 | Copper-containing plug for connection of semiconductor surface with overlying conductor | Jan 26, 1998 | Issued |
| 09/014140 | THERMALLY CONDUCTIVE FILM AND METHOD FOR THE PREPARATION THEREOF | Jan 26, 1998 | Abandoned |
Array
(
[id] => 3980391
[patent_doc_number] => 05905281
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Draw cell with a fork-shaped capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/013690
[patent_app_country] => US
[patent_app_date] => 1998-01-26
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[firstpage_image] =>[orig_patent_app_number] => 013690
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/013690 | Draw cell with a fork-shaped capacitor | Jan 25, 1998 | Issued |