
David B. Hardy
Examiner (ID: 2576)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2826, 2508 |
| Total Applications | 965 |
| Issued Applications | 799 |
| Pending Applications | 23 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4009921
[patent_doc_number] => 05859448
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Alternative silicon chip geometries for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/921856
[patent_app_country] => US
[patent_app_date] => 1997-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6556
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/859/05859448.pdf
[firstpage_image] =>[orig_patent_app_number] => 921856
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/921856 | Alternative silicon chip geometries for integrated circuits | Sep 1, 1997 | Issued |
Array
(
[id] => 3812003
[patent_doc_number] => 05854496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-29
[patent_title] => 'Hydrogen-terminated diamond misfet and its manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 8/919792
[patent_app_country] => US
[patent_app_date] => 1997-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 5237
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
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[pdf_file] => patents/05/854/05854496.pdf
[firstpage_image] =>[orig_patent_app_number] => 919792
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/919792 | Hydrogen-terminated diamond misfet and its manufacturing method | Aug 28, 1997 | Issued |
Array
(
[id] => 3987490
[patent_doc_number] => 05861648
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Capacitor unit of a booster circuit whose low-voltage operating point margin can be expanded while an increase in area occupied thereby is suppressed'
[patent_app_type] => 1
[patent_app_number] => 8/917748
[patent_app_country] => US
[patent_app_date] => 1997-08-27
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3971
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[pdf_file] => patents/05/861/05861648.pdf
[firstpage_image] =>[orig_patent_app_number] => 917748
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/917748 | Capacitor unit of a booster circuit whose low-voltage operating point margin can be expanded while an increase in area occupied thereby is suppressed | Aug 26, 1997 | Issued |
Array
(
[id] => 4041920
[patent_doc_number] => 05856701
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Dielectrically isolated power semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/921726
[patent_app_country] => US
[patent_app_date] => 1997-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2130
[patent_no_of_claims] => 16
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[firstpage_image] =>[orig_patent_app_number] => 921726
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/921726 | Dielectrically isolated power semiconductor devices | Aug 26, 1997 | Issued |
Array
(
[id] => 4003111
[patent_doc_number] => 05923091
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Bonded semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/917342
[patent_app_country] => US
[patent_app_date] => 1997-08-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/923/05923091.pdf
[firstpage_image] =>[orig_patent_app_number] => 917342
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/917342 | Bonded semiconductor integrated circuit device | Aug 25, 1997 | Issued |
Array
(
[id] => 3964525
[patent_doc_number] => 05900660
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls'
[patent_app_type] => 1
[patent_app_number] => 8/916863
[patent_app_country] => US
[patent_app_date] => 1997-08-22
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2195
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[pdf_file] => patents/05/900/05900660.pdf
[firstpage_image] =>[orig_patent_app_number] => 916863
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916863 | Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls | Aug 21, 1997 | Issued |
Array
(
[id] => 4002673
[patent_doc_number] => 05923060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Reduced area gate array cell design based on shifted placement of alternate rows of cells'
[patent_app_type] => 1
[patent_app_number] => 8/917006
[patent_app_country] => US
[patent_app_date] => 1997-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 3147
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[pdf_file] => patents/05/923/05923060.pdf
[firstpage_image] =>[orig_patent_app_number] => 917006
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/917006 | Reduced area gate array cell design based on shifted placement of alternate rows of cells | Aug 20, 1997 | Issued |
Array
(
[id] => 4123486
[patent_doc_number] => 06072218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Low capacitance input/output integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/912942
[patent_app_country] => US
[patent_app_date] => 1997-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 6474
[patent_no_of_claims] => 8
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[pdf_file] => patents/06/072/06072218.pdf
[firstpage_image] =>[orig_patent_app_number] => 912942
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/912942 | Low capacitance input/output integrated circuit | Aug 17, 1997 | Issued |
Array
(
[id] => 3812726
[patent_doc_number] => 05831334
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon'
[patent_app_type] => 1
[patent_app_number] => 8/912899
[patent_app_country] => US
[patent_app_date] => 1997-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2560
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[pdf_file] => patents/05/831/05831334.pdf
[firstpage_image] =>[orig_patent_app_number] => 912899
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/912899 | Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon | Aug 14, 1997 | Issued |
Array
(
[id] => 4031755
[patent_doc_number] => 05903044
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Hermetic chip and method of manufacture'
[patent_app_type] => 1
[patent_app_number] => 8/910613
[patent_app_country] => US
[patent_app_date] => 1997-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5010
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[pdf_file] => patents/05/903/05903044.pdf
[firstpage_image] =>[orig_patent_app_number] => 910613
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/910613 | Hermetic chip and method of manufacture | Aug 12, 1997 | Issued |
Array
(
[id] => 4145379
[patent_doc_number] => 06060760
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Optimal resistor network layout'
[patent_app_type] => 1
[patent_app_number] => 8/910269
[patent_app_country] => US
[patent_app_date] => 1997-08-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/060/06060760.pdf
[firstpage_image] =>[orig_patent_app_number] => 910269
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/910269 | Optimal resistor network layout | Aug 12, 1997 | Issued |
Array
(
[id] => 4224570
[patent_doc_number] => 06040600
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Trenched high breakdown voltage semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/909411
[patent_app_country] => US
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[pdf_file] => patents/06/040/06040600.pdf
[firstpage_image] =>[orig_patent_app_number] => 909411
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/909411 | Trenched high breakdown voltage semiconductor device | Aug 10, 1997 | Issued |
Array
(
[id] => 4013396
[patent_doc_number] => 05889308
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Semiconductor device having an electrostatic discharging protection circuit using a non-ohmic material'
[patent_app_type] => 1
[patent_app_number] => 8/907854
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[patent_app_date] => 1997-08-08
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[pdf_file] => patents/05/889/05889308.pdf
[firstpage_image] =>[orig_patent_app_number] => 907854
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/907854 | Semiconductor device having an electrostatic discharging protection circuit using a non-ohmic material | Aug 7, 1997 | Issued |
Array
(
[id] => 4030592
[patent_doc_number] => 05883409
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'EEPROM with split gate source side injection'
[patent_app_type] => 1
[patent_app_number] => 8/908744
[patent_app_country] => US
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[pdf_file] => patents/05/883/05883409.pdf
[firstpage_image] =>[orig_patent_app_number] => 908744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/908744 | EEPROM with split gate source side injection | Aug 6, 1997 | Issued |
Array
(
[id] => 3799582
[patent_doc_number] => 05780909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Semiconductor memory device with a two-layer top gate'
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[patent_app_number] => 8/905334
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[pdf_file] => patents/05/780/05780909.pdf
[firstpage_image] =>[orig_patent_app_number] => 905334
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905334 | Semiconductor memory device with a two-layer top gate | Aug 3, 1997 | Issued |
Array
(
[id] => 4027087
[patent_doc_number] => 05925918
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Gate stack with improved sidewall integrity'
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[patent_app_number] => 8/902808
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[pdf_file] => patents/05/925/05925918.pdf
[firstpage_image] =>[orig_patent_app_number] => 902808
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902808 | Gate stack with improved sidewall integrity | Jul 29, 1997 | Issued |
Array
(
[id] => 3989897
[patent_doc_number] => 05959341
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Thermoelectric semiconductor having a sintered semiconductor layer and fabrication process thereof'
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[patent_app_number] => 8/901791
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[firstpage_image] =>[orig_patent_app_number] => 901791
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/901791 | Thermoelectric semiconductor having a sintered semiconductor layer and fabrication process thereof | Jul 27, 1997 | Issued |
Array
(
[id] => 4132465
[patent_doc_number] => 06127710
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[patent_issue_date] => 2000-10-03
[patent_title] => 'CMOS structure having a gate without spacers'
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[firstpage_image] =>[orig_patent_app_number] => 900811
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/900811 | CMOS structure having a gate without spacers | Jul 24, 1997 | Issued |
Array
(
[id] => 3972446
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[patent_issue_date] => 1999-03-23
[patent_title] => 'Semiconductor component with linear current to voltage characteristics'
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[pdf_file] => patents/05/886/05886384.pdf
[firstpage_image] =>[orig_patent_app_number] => 900110
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/900110 | Semiconductor component with linear current to voltage characteristics | Jul 24, 1997 | Issued |
Array
(
[id] => 3987955
[patent_doc_number] => 05861679
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[patent_title] => 'Pattern and method for measuring alignment error'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/861/05861679.pdf
[firstpage_image] =>[orig_patent_app_number] => 899863
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/899863 | Pattern and method for measuring alignment error | Jul 23, 1997 | Issued |