David B. Hardy

Array ( [id] => 3987955 [patent_doc_number] => 05861679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Pattern and method for measuring alignment error' [patent_app_type] => 1 [patent_app_number] => 8/899863 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4451 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/861/05861679.pdf [firstpage_image] =>[orig_patent_app_number] => 899863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3812089 [patent_doc_number] => 05854502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Non-volatile memory cell having floating gate electrode and reduced bird\'s beak portions' [patent_app_type] => 1 [patent_app_number] => 8/897528 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2735 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854502.pdf [firstpage_image] =>[orig_patent_app_number] => 897528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4227712 [patent_doc_number] => 06011297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Use of multiple slots surrounding base region of a bipolar junction transistor to increase cumulative breakdown voltage' [patent_app_type] => 1 [patent_app_number] => 8/897167 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4470 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011297.pdf [firstpage_image] =>[orig_patent_app_number] => 897167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4056214 [patent_doc_number] => 05969402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Reduction of depletion spreading sideways utilizing slots' [patent_app_type] => 1 [patent_app_number] => 8/897165 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4652 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969402.pdf [firstpage_image] =>[orig_patent_app_number] => 897165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4049367 [patent_doc_number] => 05912501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Elimination of radius of curvature effects of p-n junction avalanche breakdown using slots' [patent_app_type] => 1 [patent_app_number] => 8/897265 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4660 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912501.pdf [firstpage_image] =>[orig_patent_app_number] => 897265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147994 [patent_doc_number] => 06031272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'MOS type semiconductor device having an impurity diffusion layer with a nonuniform impurity concentration profile in a channel region' [patent_app_type] => 1 [patent_app_number] => 8/836903 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 49 [patent_no_of_words] => 23270 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031272.pdf [firstpage_image] =>[orig_patent_app_number] => 836903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3939341 [patent_doc_number] => 05939789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Multilayer substrates methods for manufacturing multilayer substrates and electronic devices' [patent_app_type] => 1 [patent_app_number] => 8/893323 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 34 [patent_no_of_words] => 7211 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939789.pdf [firstpage_image] =>[orig_patent_app_number] => 893323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3844889 [patent_doc_number] => 05847421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Logic cell having efficient optical proximity effect correction' [patent_app_type] => 1 [patent_app_number] => 8/891842 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 7153 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847421.pdf [firstpage_image] =>[orig_patent_app_number] => 891842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4055817 [patent_doc_number] => 05969378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Latch-up free power UMOS-bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/891221 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6950 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969378.pdf [firstpage_image] =>[orig_patent_app_number] => 891221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4087290 [patent_doc_number] => 06054774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Thin type semiconductor package' [patent_app_type] => 1 [patent_app_number] => 8/890633 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4143 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054774.pdf [firstpage_image] =>[orig_patent_app_number] => 890633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3984788 [patent_doc_number] => 05949106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'FET input/output pad layout' [patent_app_type] => 1 [patent_app_number] => 8/887905 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1822 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949106.pdf [firstpage_image] =>[orig_patent_app_number] => 887905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3882382 [patent_doc_number] => 05804838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Thin film transistors' [patent_app_type] => 1 [patent_app_number] => 8/887516 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2526 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804838.pdf [firstpage_image] =>[orig_patent_app_number] => 887516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932000 [patent_doc_number] => 05952709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'High-frequency semiconductor device and mounted structure thereof' [patent_app_type] => 1 [patent_app_number] => 8/884223 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7868 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952709.pdf [firstpage_image] =>[orig_patent_app_number] => 884223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3788341 [patent_doc_number] => 05821584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Thin film transistors comprising drain offset regions' [patent_app_type] => 1 [patent_app_number] => 8/883756 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2566 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821584.pdf [firstpage_image] =>[orig_patent_app_number] => 883756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4010197 [patent_doc_number] => 05859467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Integrated circuit memory devices having improved supply line connections, and methods of forming same' [patent_app_type] => 1 [patent_app_number] => 8/883878 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2686 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859467.pdf [firstpage_image] =>[orig_patent_app_number] => 883878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944876 [patent_doc_number] => 05973408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Electrode structure for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/882191 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6378 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973408.pdf [firstpage_image] =>[orig_patent_app_number] => 882191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4049185 [patent_doc_number] => 05912488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming' [patent_app_type] => 1 [patent_app_number] => 8/881444 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 8646 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912488.pdf [firstpage_image] =>[orig_patent_app_number] => 881444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139505 [patent_doc_number] => 06121645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Noise-reducing circuit' [patent_app_type] => 1 [patent_app_number] => 8/881500 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4005 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121645.pdf [firstpage_image] =>[orig_patent_app_number] => 881500 [rel_patent_id] =>[rel_patent_doc_number] =>)