
David B. Hardy
Examiner (ID: 8256)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2826, 2815, 2508 |
| Total Applications | 965 |
| Issued Applications | 799 |
| Pending Applications | 23 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3929727
[patent_doc_number] => 05945738
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Dual landing pad structure in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/760098
[patent_app_country] => US
[patent_app_date] => 1996-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4064
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/945/05945738.pdf
[firstpage_image] =>[orig_patent_app_number] => 760098
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760098 | Dual landing pad structure in an integrated circuit | Dec 2, 1996 | Issued |
Array
(
[id] => 3830166
[patent_doc_number] => 05731614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Electrostatic protective device having elongate gate electrodes in a ladder structure'
[patent_app_type] => 1
[patent_app_number] => 8/752960
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2111
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/731/05731614.pdf
[firstpage_image] =>[orig_patent_app_number] => 752960
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/752960 | Electrostatic protective device having elongate gate electrodes in a ladder structure | Dec 1, 1996 | Issued |
Array
(
[id] => 3750913
[patent_doc_number] => 05717252
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Solder-ball connected semiconductor device with a recessed chip mounting area'
[patent_app_type] => 1
[patent_app_number] => 8/757639
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 35
[patent_no_of_words] => 9457
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717252.pdf
[firstpage_image] =>[orig_patent_app_number] => 757639
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757639 | Solder-ball connected semiconductor device with a recessed chip mounting area | Dec 1, 1996 | Issued |
Array
(
[id] => 3761299
[patent_doc_number] => 05721451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Integrated circuit assembly adhesive and method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/758660
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1895
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721451.pdf
[firstpage_image] =>[orig_patent_app_number] => 758660
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758660 | Integrated circuit assembly adhesive and method thereof | Dec 1, 1996 | Issued |
Array
(
[id] => 3998590
[patent_doc_number] => 05892282
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Barrier-less plug structure'
[patent_app_type] => 1
[patent_app_number] => 8/757776
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3223
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892282.pdf
[firstpage_image] =>[orig_patent_app_number] => 757776
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757776 | Barrier-less plug structure | Nov 26, 1996 | Issued |
Array
(
[id] => 4013353
[patent_doc_number] => 05889305
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Non-volatile semiconductor memory device having storage cell array and peripheral circuit'
[patent_app_type] => 1
[patent_app_number] => 8/753684
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 5388
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/889/05889305.pdf
[firstpage_image] =>[orig_patent_app_number] => 753684
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/753684 | Non-volatile semiconductor memory device having storage cell array and peripheral circuit | Nov 26, 1996 | Issued |
Array
(
[id] => 3844721
[patent_doc_number] => 05847410
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Semiconductor electro-optical device'
[patent_app_type] => 1
[patent_app_number] => 8/756172
[patent_app_country] => US
[patent_app_date] => 1996-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 34
[patent_no_of_words] => 7055
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/847/05847410.pdf
[firstpage_image] =>[orig_patent_app_number] => 756172
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756172 | Semiconductor electro-optical device | Nov 24, 1996 | Issued |
Array
(
[id] => 3779905
[patent_doc_number] => 05757031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Semiconductor static memory device having a TFT load'
[patent_app_type] => 1
[patent_app_number] => 8/755777
[patent_app_country] => US
[patent_app_date] => 1996-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 8783
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/757/05757031.pdf
[firstpage_image] =>[orig_patent_app_number] => 755777
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/755777 | Semiconductor static memory device having a TFT load | Nov 21, 1996 | Issued |
Array
(
[id] => 4037789
[patent_doc_number] => 05994730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'DRAM cell having storage capacitor contact self-aligned to bit lines and word lines'
[patent_app_type] => 1
[patent_app_number] => 8/754391
[patent_app_country] => US
[patent_app_date] => 1996-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 29
[patent_no_of_words] => 5870
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 306
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994730.pdf
[firstpage_image] =>[orig_patent_app_number] => 754391
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754391 | DRAM cell having storage capacitor contact self-aligned to bit lines and word lines | Nov 20, 1996 | Issued |
Array
(
[id] => 3765838
[patent_doc_number] => 05742095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Method of fabricating planar regions in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/752749
[patent_app_country] => US
[patent_app_date] => 1996-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 4129
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742095.pdf
[firstpage_image] =>[orig_patent_app_number] => 752749
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/752749 | Method of fabricating planar regions in an integrated circuit | Nov 19, 1996 | Issued |
Array
(
[id] => 4038660
[patent_doc_number] => 05942787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Small gate electrode MOSFET'
[patent_app_type] => 1
[patent_app_number] => 8/751582
[patent_app_country] => US
[patent_app_date] => 1996-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2247
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/942/05942787.pdf
[firstpage_image] =>[orig_patent_app_number] => 751582
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/751582 | Small gate electrode MOSFET | Nov 17, 1996 | Issued |
Array
(
[id] => 4030678
[patent_doc_number] => 05883415
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'CMOS semiconductor device with improved layout of transistors near LCD drive terminals'
[patent_app_type] => 1
[patent_app_number] => 8/749942
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 2995
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/883/05883415.pdf
[firstpage_image] =>[orig_patent_app_number] => 749942
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749942 | CMOS semiconductor device with improved layout of transistors near LCD drive terminals | Nov 13, 1996 | Issued |
Array
(
[id] => 3736225
[patent_doc_number] => 05665990
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Metal oxide semiconductor device with self-aligned groove channel and method for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/749153
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2490
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/665/05665990.pdf
[firstpage_image] =>[orig_patent_app_number] => 749153
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749153 | Metal oxide semiconductor device with self-aligned groove channel and method for manufacturing the same | Nov 13, 1996 | Issued |
Array
(
[id] => 3821279
[patent_doc_number] => 05770876
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Semiconductor trench capacitor cell having a buried strap'
[patent_app_type] => 1
[patent_app_number] => 8/748961
[patent_app_country] => US
[patent_app_date] => 1996-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 4557
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/770/05770876.pdf
[firstpage_image] =>[orig_patent_app_number] => 748961
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/748961 | Semiconductor trench capacitor cell having a buried strap | Nov 12, 1996 | Issued |
| 08/745872 | SEMICONDUCTOR DEVICE USING SINGLE CRYSTAL SEMICONDUCTOR LAYER ON AN INSULATING LAYER AND MANUFACTURE METHOD OF SAME | Nov 7, 1996 | Abandoned |
Array
(
[id] => 3999211
[patent_doc_number] => 05920108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Late process method and apparatus for trench isolation'
[patent_app_type] => 1
[patent_app_number] => 8/745104
[patent_app_country] => US
[patent_app_date] => 1996-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 4175
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920108.pdf
[firstpage_image] =>[orig_patent_app_number] => 745104
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/745104 | Late process method and apparatus for trench isolation | Nov 6, 1996 | Issued |
Array
(
[id] => 3799212
[patent_doc_number] => 05780884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Amplication type solid-state imaging device'
[patent_app_type] => 1
[patent_app_number] => 8/744618
[patent_app_country] => US
[patent_app_date] => 1996-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 11216
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/780/05780884.pdf
[firstpage_image] =>[orig_patent_app_number] => 744618
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744618 | Amplication type solid-state imaging device | Nov 5, 1996 | Issued |
Array
(
[id] => 3775925
[patent_doc_number] => 05850090
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Dynamic semiconductor memory device on SOI substrate'
[patent_app_type] => 1
[patent_app_number] => 8/744677
[patent_app_country] => US
[patent_app_date] => 1996-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3938
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 343
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/850/05850090.pdf
[firstpage_image] =>[orig_patent_app_number] => 744677
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744677 | Dynamic semiconductor memory device on SOI substrate | Nov 5, 1996 | Issued |
Array
(
[id] => 4140880
[patent_doc_number] => 06016012
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Thin liner layer providing reduced via resistance'
[patent_app_type] => 1
[patent_app_number] => 8/744248
[patent_app_country] => US
[patent_app_date] => 1996-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 3527
[patent_no_of_claims] => 24
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/016/06016012.pdf
[firstpage_image] =>[orig_patent_app_number] => 744248
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744248 | Thin liner layer providing reduced via resistance | Nov 4, 1996 | Issued |
Array
(
[id] => 3939147
[patent_doc_number] => 05939775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Leadframe structure and process for packaging intergrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/744520
[patent_app_country] => US
[patent_app_date] => 1996-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 6177
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/939/05939775.pdf
[firstpage_image] =>[orig_patent_app_number] => 744520
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744520 | Leadframe structure and process for packaging intergrated circuits | Nov 4, 1996 | Issued |