| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3845602
[patent_doc_number] => 05744854
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Surge protective device having a surface collector region directly shorted to a base region'
[patent_app_type] => 1
[patent_app_number] => 8/694828
[patent_app_country] => US
[patent_app_date] => 1996-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4271
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/744/05744854.pdf
[firstpage_image] =>[orig_patent_app_number] => 694828
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/694828 | Surge protective device having a surface collector region directly shorted to a base region | Aug 8, 1996 | Issued |
Array
(
[id] => 3972560
[patent_doc_number] => 05886392
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'One-time programmable element having controlled programmed state resistance'
[patent_app_type] => 1
[patent_app_number] => 8/694168
[patent_app_country] => US
[patent_app_date] => 1996-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 3048
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/886/05886392.pdf
[firstpage_image] =>[orig_patent_app_number] => 694168
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/694168 | One-time programmable element having controlled programmed state resistance | Aug 7, 1996 | Issued |
Array
(
[id] => 3633184
[patent_doc_number] => 05686747
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Integrated circuits comprising interconnecting plugs'
[patent_app_type] => 1
[patent_app_number] => 8/700320
[patent_app_country] => US
[patent_app_date] => 1996-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 3172
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/686/05686747.pdf
[firstpage_image] =>[orig_patent_app_number] => 700320
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/700320 | Integrated circuits comprising interconnecting plugs | Aug 6, 1996 | Issued |
Array
(
[id] => 3933475
[patent_doc_number] => 05877559
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Film carrier for fine-pitched and high density mounting and semiconductor device using same'
[patent_app_type] => 1
[patent_app_number] => 8/689234
[patent_app_country] => US
[patent_app_date] => 1996-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5714
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/877/05877559.pdf
[firstpage_image] =>[orig_patent_app_number] => 689234
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/689234 | Film carrier for fine-pitched and high density mounting and semiconductor device using same | Aug 5, 1996 | Issued |
Array
(
[id] => 3861958
[patent_doc_number] => 05705838
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Array of bit line over capacitor array of memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/692748
[patent_app_country] => US
[patent_app_date] => 1996-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2192
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/705/05705838.pdf
[firstpage_image] =>[orig_patent_app_number] => 692748
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/692748 | Array of bit line over capacitor array of memory cells | Aug 5, 1996 | Issued |
Array
(
[id] => 3745494
[patent_doc_number] => 05753968
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Low loss ridged microstrip line for monolithic microwave integrated circuit (MMIC) applications'
[patent_app_type] => 1
[patent_app_number] => 8/693868
[patent_app_country] => US
[patent_app_date] => 1996-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1847
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/753/05753968.pdf
[firstpage_image] =>[orig_patent_app_number] => 693868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/693868 | Low loss ridged microstrip line for monolithic microwave integrated circuit (MMIC) applications | Aug 4, 1996 | Issued |
Array
(
[id] => 3693034
[patent_doc_number] => 05663578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Thin film transistor with self-aligned bottom gate'
[patent_app_type] => 1
[patent_app_number] => 8/690882
[patent_app_country] => US
[patent_app_date] => 1996-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2811
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/663/05663578.pdf
[firstpage_image] =>[orig_patent_app_number] => 690882
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/690882 | Thin film transistor with self-aligned bottom gate | Aug 1, 1996 | Issued |
Array
(
[id] => 3780088
[patent_doc_number] => 05757043
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Charge pump semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/691870
[patent_app_country] => US
[patent_app_date] => 1996-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2525
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/757/05757043.pdf
[firstpage_image] =>[orig_patent_app_number] => 691870
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/691870 | Charge pump semiconductor device | Aug 1, 1996 | Issued |
Array
(
[id] => 4016972
[patent_doc_number] => 05962889
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Nonvolatile semiconductor memory with a floating gate that has a bottom surface that is smaller than the upper surface'
[patent_app_type] => 1
[patent_app_number] => 8/690621
[patent_app_country] => US
[patent_app_date] => 1996-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 38
[patent_no_of_words] => 6649
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/962/05962889.pdf
[firstpage_image] =>[orig_patent_app_number] => 690621
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/690621 | Nonvolatile semiconductor memory with a floating gate that has a bottom surface that is smaller than the upper surface | Jul 30, 1996 | Issued |
Array
(
[id] => 3864347
[patent_doc_number] => 05793058
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Multi-gate offset source and drain field effect transistors and methods of operating same'
[patent_app_type] => 1
[patent_app_number] => 8/692924
[patent_app_country] => US
[patent_app_date] => 1996-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 3110
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793058.pdf
[firstpage_image] =>[orig_patent_app_number] => 692924
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/692924 | Multi-gate offset source and drain field effect transistors and methods of operating same | Jul 30, 1996 | Issued |
Array
(
[id] => 3896526
[patent_doc_number] => 05834847
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Completely buried contact holes'
[patent_app_type] => 1
[patent_app_number] => 8/688606
[patent_app_country] => US
[patent_app_date] => 1996-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3800
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/834/05834847.pdf
[firstpage_image] =>[orig_patent_app_number] => 688606
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/688606 | Completely buried contact holes | Jul 29, 1996 | Issued |
| 08/688523 | DIELECTRICALLY ISOLATED WELL STRUCTURES | Jul 29, 1996 | Abandoned |
Array
(
[id] => 3728382
[patent_doc_number] => 05672909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Interdigitated wirebond programmable fixed voltage planes'
[patent_app_type] => 1
[patent_app_number] => 8/688083
[patent_app_country] => US
[patent_app_date] => 1996-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3152
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/672/05672909.pdf
[firstpage_image] =>[orig_patent_app_number] => 688083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/688083 | Interdigitated wirebond programmable fixed voltage planes | Jul 28, 1996 | Issued |
Array
(
[id] => 3799118
[patent_doc_number] => 05780878
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Lateral gate, vertical drift region transistor'
[patent_app_type] => 1
[patent_app_number] => 8/681684
[patent_app_country] => US
[patent_app_date] => 1996-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2679
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/780/05780878.pdf
[firstpage_image] =>[orig_patent_app_number] => 681684
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/681684 | Lateral gate, vertical drift region transistor | Jul 28, 1996 | Issued |
| 08/688222 | SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD OF SAME | Jul 28, 1996 | Abandoned |
| 08/682660 | THIN FILM TRANSISTOR FOR LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME | Jul 28, 1996 | Abandoned |
| 08/687830 | THIN FILM OR SOLDER BALL INCLUDING A METAL AND AN OXIDE, NITRIDE, OR CARBIDE PRECIPITATE OF AN EXPANDABLE OR CONTRACTIBLE ELEMENT | Jul 25, 1996 | Abandoned |
Array
(
[id] => 4222950
[patent_doc_number] => 06087710
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Semiconductor device having self-aligned contacts'
[patent_app_type] => 1
[patent_app_number] => 8/687624
[patent_app_country] => US
[patent_app_date] => 1996-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 33
[patent_no_of_words] => 16555
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/087/06087710.pdf
[firstpage_image] =>[orig_patent_app_number] => 687624
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/687624 | Semiconductor device having self-aligned contacts | Jul 25, 1996 | Issued |
Array
(
[id] => 3865543
[patent_doc_number] => 05796128
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Gate array with fully wired multiplexer circuits'
[patent_app_type] => 1
[patent_app_number] => 8/695068
[patent_app_country] => US
[patent_app_date] => 1996-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3967
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/796/05796128.pdf
[firstpage_image] =>[orig_patent_app_number] => 695068
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/695068 | Gate array with fully wired multiplexer circuits | Jul 24, 1996 | Issued |
Array
(
[id] => 3880239
[patent_doc_number] => 05825076
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Integrated circuit non-etch technique for forming vias in a semiconductor wafer and a semiconductor wafer having vias formed therein using non-etch technique'
[patent_app_type] => 1
[patent_app_number] => 8/685884
[patent_app_country] => US
[patent_app_date] => 1996-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825076.pdf
[firstpage_image] =>[orig_patent_app_number] => 685884
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/685884 | Integrated circuit non-etch technique for forming vias in a semiconductor wafer and a semiconductor wafer having vias formed therein using non-etch technique | Jul 24, 1996 | Issued |