
David B. Hardy
Examiner (ID: 1866)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2826, 2508 |
| Total Applications | 965 |
| Issued Applications | 799 |
| Pending Applications | 23 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3980545
[patent_doc_number] => 05905292
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/129836
[patent_app_country] => US
[patent_app_date] => 1998-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 87
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[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
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[pdf_file] => patents/05/905/05905292.pdf
[firstpage_image] =>[orig_patent_app_number] => 129836
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/129836 | Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same | Aug 5, 1998 | Issued |
Array
(
[id] => 4161018
[patent_doc_number] => 06107651
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Gate turn-off thyristor with stop layer'
[patent_app_type] => 1
[patent_app_number] => 9/124892
[patent_app_country] => US
[patent_app_date] => 1998-07-30
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[pdf_file] => patents/06/107/06107651.pdf
[firstpage_image] =>[orig_patent_app_number] => 124892
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Array
(
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[patent_doc_number] => 06130472
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[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Moisture and ion barrier for protection of devices and interconnect structures'
[patent_app_type] => 1
[patent_app_number] => 9/122353
[patent_app_country] => US
[patent_app_date] => 1998-07-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/122353 | Moisture and ion barrier for protection of devices and interconnect structures | Jul 23, 1998 | Issued |
Array
(
[id] => 4145616
[patent_doc_number] => 06060777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Underside heat slug for ball grid array packages'
[patent_app_type] => 1
[patent_app_number] => 9/119863
[patent_app_country] => US
[patent_app_date] => 1998-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 1358
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[firstpage_image] =>[orig_patent_app_number] => 119863
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/119863 | Underside heat slug for ball grid array packages | Jul 20, 1998 | Issued |
Array
(
[id] => 4203273
[patent_doc_number] => 06013923
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[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'Semiconductor switch array with electrostatic discharge protection and method of fabricating'
[patent_app_type] => 1
[patent_app_number] => 9/000479
[patent_app_country] => US
[patent_app_date] => 1998-07-21
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[firstpage_image] =>[orig_patent_app_number] => 000479
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/000479 | Semiconductor switch array with electrostatic discharge protection and method of fabricating | Jul 20, 1998 | Issued |
Array
(
[id] => 4075710
[patent_doc_number] => 06069372
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Insulated gate type semiconductor device with potential detection gate for overvoltage protection'
[patent_app_type] => 1
[patent_app_number] => 9/116342
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[patent_app_date] => 1998-07-16
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[firstpage_image] =>[orig_patent_app_number] => 116342
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/116342 | Insulated gate type semiconductor device with potential detection gate for overvoltage protection | Jul 15, 1998 | Issued |
Array
(
[id] => 4309285
[patent_doc_number] => 06188091
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[patent_issue_date] => 2001-02-13
[patent_title] => 'FPGA one turn routing structure using minimum diffusion area'
[patent_app_type] => 1
[patent_app_number] => 9/116292
[patent_app_country] => US
[patent_app_date] => 1998-07-16
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[firstpage_image] =>[orig_patent_app_number] => 116292
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/116292 | FPGA one turn routing structure using minimum diffusion area | Jul 15, 1998 | Issued |
Array
(
[id] => 4364605
[patent_doc_number] => 06191463
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Apparatus and method of improving an insulating film on a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/115233
[patent_app_country] => US
[patent_app_date] => 1998-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
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[pdf_file] => patents/06/191/06191463.pdf
[firstpage_image] =>[orig_patent_app_number] => 115233
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/115233 | Apparatus and method of improving an insulating film on a semiconductor device | Jul 13, 1998 | Issued |
Array
(
[id] => 4196169
[patent_doc_number] => 06130446
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[patent_issue_date] => 2000-10-10
[patent_title] => 'Electrode of n-type nitridide semiconductor, semiconductor device having the electrode, and method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/113301
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[firstpage_image] =>[orig_patent_app_number] => 113301
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/113301 | Electrode of n-type nitridide semiconductor, semiconductor device having the electrode, and method of fabricating the same | Jul 9, 1998 | Issued |
Array
(
[id] => 3929543
[patent_doc_number] => 05945725
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Spherical shaped integrated circuit utilizing an inductor'
[patent_app_type] => 1
[patent_app_number] => 9/112839
[patent_app_country] => US
[patent_app_date] => 1998-07-10
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[firstpage_image] =>[orig_patent_app_number] => 112839
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/112839 | Spherical shaped integrated circuit utilizing an inductor | Jul 9, 1998 | Issued |
Array
(
[id] => 4190754
[patent_doc_number] => 06093945
[patent_country] => US
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[patent_issue_date] => 2000-07-25
[patent_title] => 'Split gate flash memory with minimum over-erase problem'
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[patent_app_number] => 9/113032
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[patent_app_date] => 1998-07-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/113032 | Split gate flash memory with minimum over-erase problem | Jul 8, 1998 | Issued |
Array
(
[id] => 4196283
[patent_doc_number] => 06130454
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[patent_issue_date] => 2000-10-10
[patent_title] => 'Gate conductor formed within a trench bounded by slanted sidewalls'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/111053 | Gate conductor formed within a trench bounded by slanted sidewalls | Jul 6, 1998 | Issued |
Array
(
[id] => 4105120
[patent_doc_number] => 06066878
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[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'High voltage semiconductor structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/108962 | High voltage semiconductor structure | Jul 1, 1998 | Issued |
Array
(
[id] => 4244055
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[patent_title] => 'Capacitance structure for preventing degradation of the insulating film'
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Array
(
[id] => 4253608
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/107823 | Preventing backside analysis of an integrated circuit | Jun 29, 1998 | Issued |
Array
(
[id] => 4362427
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[patent_issue_date] => 2001-01-16
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Array
(
[id] => 4243953
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Array
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Array
(
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Array
(
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[pdf_file] => patents/06/127/06127711.pdf
[firstpage_image] =>[orig_patent_app_number] => 102363
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/102363 | Semiconductor device having plural air gaps for decreasing parasitic capacitance | Jun 22, 1998 | Issued |