Search

David B. Hardy

Examiner (ID: 1866)

Most Active Art Unit
2815
Art Unit(s)
2815, 2826, 2508
Total Applications
965
Issued Applications
799
Pending Applications
23
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3980545 [patent_doc_number] => 05905292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/129836 [patent_app_country] => US [patent_app_date] => 1998-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 87 [patent_no_of_words] => 14503 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905292.pdf [firstpage_image] =>[orig_patent_app_number] => 129836 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129836
Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same Aug 5, 1998 Issued
Array ( [id] => 4161018 [patent_doc_number] => 06107651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Gate turn-off thyristor with stop layer' [patent_app_type] => 1 [patent_app_number] => 9/124892 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1384 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107651.pdf [firstpage_image] =>[orig_patent_app_number] => 124892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124892
Gate turn-off thyristor with stop layer Jul 29, 1998 Issued
Array ( [id] => 4196540 [patent_doc_number] => 06130472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Moisture and ion barrier for protection of devices and interconnect structures' [patent_app_type] => 1 [patent_app_number] => 9/122353 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4024 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130472.pdf [firstpage_image] =>[orig_patent_app_number] => 122353 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122353
Moisture and ion barrier for protection of devices and interconnect structures Jul 23, 1998 Issued
Array ( [id] => 4145616 [patent_doc_number] => 06060777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Underside heat slug for ball grid array packages' [patent_app_type] => 1 [patent_app_number] => 9/119863 [patent_app_country] => US [patent_app_date] => 1998-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1358 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060777.pdf [firstpage_image] =>[orig_patent_app_number] => 119863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/119863
Underside heat slug for ball grid array packages Jul 20, 1998 Issued
Array ( [id] => 4203273 [patent_doc_number] => 06013923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Semiconductor switch array with electrostatic discharge protection and method of fabricating' [patent_app_type] => 1 [patent_app_number] => 9/000479 [patent_app_country] => US [patent_app_date] => 1998-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013923.pdf [firstpage_image] =>[orig_patent_app_number] => 000479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000479
Semiconductor switch array with electrostatic discharge protection and method of fabricating Jul 20, 1998 Issued
Array ( [id] => 4075710 [patent_doc_number] => 06069372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Insulated gate type semiconductor device with potential detection gate for overvoltage protection' [patent_app_type] => 1 [patent_app_number] => 9/116342 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069372.pdf [firstpage_image] =>[orig_patent_app_number] => 116342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116342
Insulated gate type semiconductor device with potential detection gate for overvoltage protection Jul 15, 1998 Issued
Array ( [id] => 4309285 [patent_doc_number] => 06188091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'FPGA one turn routing structure using minimum diffusion area' [patent_app_type] => 1 [patent_app_number] => 9/116292 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3911 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188091.pdf [firstpage_image] =>[orig_patent_app_number] => 116292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116292
FPGA one turn routing structure using minimum diffusion area Jul 15, 1998 Issued
Array ( [id] => 4364605 [patent_doc_number] => 06191463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Apparatus and method of improving an insulating film on a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/115233 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 257 [patent_no_of_words] => 25462 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191463.pdf [firstpage_image] =>[orig_patent_app_number] => 115233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115233
Apparatus and method of improving an insulating film on a semiconductor device Jul 13, 1998 Issued
Array ( [id] => 4196169 [patent_doc_number] => 06130446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Electrode of n-type nitridide semiconductor, semiconductor device having the electrode, and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/113301 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5015 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130446.pdf [firstpage_image] =>[orig_patent_app_number] => 113301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113301
Electrode of n-type nitridide semiconductor, semiconductor device having the electrode, and method of fabricating the same Jul 9, 1998 Issued
Array ( [id] => 3929543 [patent_doc_number] => 05945725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Spherical shaped integrated circuit utilizing an inductor' [patent_app_type] => 1 [patent_app_number] => 9/112839 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1293 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945725.pdf [firstpage_image] =>[orig_patent_app_number] => 112839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112839
Spherical shaped integrated circuit utilizing an inductor Jul 9, 1998 Issued
Array ( [id] => 4190754 [patent_doc_number] => 06093945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Split gate flash memory with minimum over-erase problem' [patent_app_type] => 1 [patent_app_number] => 9/113032 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4569 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093945.pdf [firstpage_image] =>[orig_patent_app_number] => 113032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113032
Split gate flash memory with minimum over-erase problem Jul 8, 1998 Issued
Array ( [id] => 4196283 [patent_doc_number] => 06130454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Gate conductor formed within a trench bounded by slanted sidewalls' [patent_app_type] => 1 [patent_app_number] => 9/111053 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5148 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130454.pdf [firstpage_image] =>[orig_patent_app_number] => 111053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111053
Gate conductor formed within a trench bounded by slanted sidewalls Jul 6, 1998 Issued
Array ( [id] => 4105120 [patent_doc_number] => 06066878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'High voltage semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 9/108962 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2432 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066878.pdf [firstpage_image] =>[orig_patent_app_number] => 108962 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108962
High voltage semiconductor structure Jul 1, 1998 Issued
Array ( [id] => 4244055 [patent_doc_number] => 06166424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Capacitance structure for preventing degradation of the insulating film' [patent_app_type] => 1 [patent_app_number] => 9/109032 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 7674 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166424.pdf [firstpage_image] =>[orig_patent_app_number] => 109032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109032
Capacitance structure for preventing degradation of the insulating film Jul 1, 1998 Issued
Array ( [id] => 4253608 [patent_doc_number] => 06137173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Preventing backside analysis of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/107823 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2423 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137173.pdf [firstpage_image] =>[orig_patent_app_number] => 107823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107823
Preventing backside analysis of an integrated circuit Jun 29, 1998 Issued
Array ( [id] => 4362427 [patent_doc_number] => 06175124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method and apparatus for a wafer level system' [patent_app_type] => 1 [patent_app_number] => 9/108092 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4176 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175124.pdf [firstpage_image] =>[orig_patent_app_number] => 108092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108092
Method and apparatus for a wafer level system Jun 29, 1998 Issued
Array ( [id] => 4243953 [patent_doc_number] => 06166417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Complementary metal gates and a process for implementation' [patent_app_type] => 1 [patent_app_number] => 9/109993 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2861 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166417.pdf [firstpage_image] =>[orig_patent_app_number] => 109993 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109993
Complementary metal gates and a process for implementation Jun 29, 1998 Issued
Array ( [id] => 3998874 [patent_doc_number] => 05920085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Multiple floating gate field effect transistors and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 9/104585 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3109 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920085.pdf [firstpage_image] =>[orig_patent_app_number] => 104585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104585
Multiple floating gate field effect transistors and methods of operating same Jun 24, 1998 Issued
Array ( [id] => 4161044 [patent_doc_number] => 06107653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization' [patent_app_type] => 1 [patent_app_number] => 9/103672 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3809 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107653.pdf [firstpage_image] =>[orig_patent_app_number] => 103672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103672
Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization Jun 22, 1998 Issued
Array ( [id] => 4132477 [patent_doc_number] => 06127711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor device having plural air gaps for decreasing parasitic capacitance' [patent_app_type] => 1 [patent_app_number] => 9/102363 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3738 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127711.pdf [firstpage_image] =>[orig_patent_app_number] => 102363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102363
Semiconductor device having plural air gaps for decreasing parasitic capacitance Jun 22, 1998 Issued
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