Search

David B. Hardy

Examiner (ID: 14073)

Most Active Art Unit
2815
Art Unit(s)
2508, 2815, 2826
Total Applications
965
Issued Applications
799
Pending Applications
23
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
09/078115 HIGH DENSITY INTERCONNECT SUBSTRATE AND METHOD OF MANUFACTURING SAME May 12, 1998 Issued
Array ( [id] => 4243675 [patent_doc_number] => 06166398 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Thin film transistors' [patent_app_type] => 1 [patent_app_number] => 9/075433 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3107 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166398.pdf [firstpage_image] =>[orig_patent_app_number] => 075433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075433
Thin film transistors May 7, 1998 Issued
Array ( [id] => 4265701 [patent_doc_number] => 06259125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Scalable high dielectric constant capacitor' [patent_app_type] => 1 [patent_app_number] => 9/073560 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4185 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259125.pdf [firstpage_image] =>[orig_patent_app_number] => 073560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073560
Scalable high dielectric constant capacitor May 5, 1998 Issued
Array ( [id] => 4158867 [patent_doc_number] => 06124613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'SOI-MOS field effect transistor that withdraws excess carrier through a carrier path silicon layer' [patent_app_type] => 1 [patent_app_number] => 9/071152 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 14916 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124613.pdf [firstpage_image] =>[orig_patent_app_number] => 071152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071152
SOI-MOS field effect transistor that withdraws excess carrier through a carrier path silicon layer May 3, 1998 Issued
Array ( [id] => 4300309 [patent_doc_number] => 06181012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Copper interconnection structure incorporating a metal seed layer' [patent_app_type] => 1 [patent_app_number] => 9/067851 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5756 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181012.pdf [firstpage_image] =>[orig_patent_app_number] => 067851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067851
Copper interconnection structure incorporating a metal seed layer Apr 26, 1998 Issued
Array ( [id] => 4145221 [patent_doc_number] => 06060749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Ultra-short channel elevated S/D MOSFETS formed on an ultra-thin SOI substrate' [patent_app_type] => 1 [patent_app_number] => 9/065472 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2826 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060749.pdf [firstpage_image] =>[orig_patent_app_number] => 065472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/065472
Ultra-short channel elevated S/D MOSFETS formed on an ultra-thin SOI substrate Apr 22, 1998 Issued
Array ( [id] => 3929127 [patent_doc_number] => 05945696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Silicon chip having mixed input/output slot structure' [patent_app_type] => 1 [patent_app_number] => 9/065471 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2340 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945696.pdf [firstpage_image] =>[orig_patent_app_number] => 065471 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/065471
Silicon chip having mixed input/output slot structure Apr 22, 1998 Issued
Array ( [id] => 4108689 [patent_doc_number] => 06051880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Base layer structure covering a hole of decreasing diameter in an insulation layer in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/061872 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 10228 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051880.pdf [firstpage_image] =>[orig_patent_app_number] => 061872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061872
Base layer structure covering a hole of decreasing diameter in an insulation layer in a semiconductor device Apr 16, 1998 Issued
Array ( [id] => 4101479 [patent_doc_number] => 06097054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Semiconductor memory device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/059260 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 4276 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097054.pdf [firstpage_image] =>[orig_patent_app_number] => 059260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059260
Semiconductor memory device and method of manufacturing the same Apr 13, 1998 Issued
Array ( [id] => 3954162 [patent_doc_number] => 05977619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Horizontal package having die supports leads formed along lead column' [patent_app_type] => 1 [patent_app_number] => 9/058772 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4306 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977619.pdf [firstpage_image] =>[orig_patent_app_number] => 058772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058772
Horizontal package having die supports leads formed along lead column Apr 12, 1998 Issued
Array ( [id] => 4137514 [patent_doc_number] => 06147379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/058803 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 14912 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147379.pdf [firstpage_image] =>[orig_patent_app_number] => 058803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058803
Semiconductor device and method for fabricating the same Apr 12, 1998 Issued
09/058281 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Apr 9, 1998 Issued
Array ( [id] => 3947340 [patent_doc_number] => 05982000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Resistive interconnect of transistor cells' [patent_app_type] => 1 [patent_app_number] => 9/055023 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1103 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982000.pdf [firstpage_image] =>[orig_patent_app_number] => 055023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055023
Resistive interconnect of transistor cells Apr 2, 1998 Issued
Array ( [id] => 4163005 [patent_doc_number] => 06114724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Nonvolatile semiconductor memory cell with select gate' [patent_app_type] => 1 [patent_app_number] => 9/052770 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6677 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114724.pdf [firstpage_image] =>[orig_patent_app_number] => 052770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052770
Nonvolatile semiconductor memory cell with select gate Mar 30, 1998 Issued
Array ( [id] => 4056285 [patent_doc_number] => 05969407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'MOSFET device with an amorphized source' [patent_app_type] => 1 [patent_app_number] => 9/050552 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6789 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969407.pdf [firstpage_image] =>[orig_patent_app_number] => 050552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050552
MOSFET device with an amorphized source Mar 29, 1998 Issued
Array ( [id] => 4187057 [patent_doc_number] => 06020613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Field effect transistor array including resistive interconnections' [patent_app_type] => 1 [patent_app_number] => 9/048891 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4504 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020613.pdf [firstpage_image] =>[orig_patent_app_number] => 048891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048891
Field effect transistor array including resistive interconnections Mar 26, 1998 Issued
Array ( [id] => 3947932 [patent_doc_number] => 05982039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Completely buried contact holes' [patent_app_type] => 1 [patent_app_number] => 9/048391 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3778 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982039.pdf [firstpage_image] =>[orig_patent_app_number] => 048391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048391
Completely buried contact holes Mar 25, 1998 Issued
Array ( [id] => 3947790 [patent_doc_number] => 05982029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor component having upper and lower mounting plates' [patent_app_type] => 1 [patent_app_number] => 9/043322 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1161 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982029.pdf [firstpage_image] =>[orig_patent_app_number] => 043322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/043322
Semiconductor component having upper and lower mounting plates Mar 19, 1998 Issued
Array ( [id] => 4239196 [patent_doc_number] => 06118157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'High voltage split gate CMOS transistors built in standard 2-poly core CMOS' [patent_app_type] => 1 [patent_app_number] => 9/044220 [patent_app_country] => US [patent_app_date] => 1998-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2213 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118157.pdf [firstpage_image] =>[orig_patent_app_number] => 044220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044220
High voltage split gate CMOS transistors built in standard 2-poly core CMOS Mar 17, 1998 Issued
Array ( [id] => 4105010 [patent_doc_number] => 06066871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Semiconductor memory device having a memory cell capacitor and a fabrication process thereof' [patent_app_type] => 1 [patent_app_number] => 9/042530 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8953 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066871.pdf [firstpage_image] =>[orig_patent_app_number] => 042530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042530
Semiconductor memory device having a memory cell capacitor and a fabrication process thereof Mar 16, 1998 Issued
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