Search

David B. Thomas

Examiner (ID: 1929, Phone: (571)272-4497 , Office: P/3723 )

Most Active Art Unit
3723
Art Unit(s)
3723
Total Applications
3255
Issued Applications
2639
Pending Applications
134
Abandoned Applications
512

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19152596 [patent_doc_number] => 11977507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => User station for a serial bus system, and method for communicating in a serial bus system [patent_app_type] => utility [patent_app_number] => 17/775505 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9852 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17775505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/775505
User station for a serial bus system, and method for communicating in a serial bus system Nov 30, 2020 Issued
Array ( [id] => 17629286 [patent_doc_number] => 20220164301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => STATUS CHECK USING SIGNALING [patent_app_type] => utility [patent_app_number] => 17/105053 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105053
Status check using signaling Nov 24, 2020 Issued
Array ( [id] => 17557967 [patent_doc_number] => 11314671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Circuit comprising a current output driver for outputting an output current to a load [patent_app_type] => utility [patent_app_number] => 17/102016 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3825 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102016
Circuit comprising a current output driver for outputting an output current to a load Nov 22, 2020 Issued
Array ( [id] => 16690671 [patent_doc_number] => 20210073149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => Direct Memory Access Data Format [patent_app_type] => utility [patent_app_number] => 16/953171 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953171
Transfer of segmented data Nov 18, 2020 Issued
Array ( [id] => 16690672 [patent_doc_number] => 20210073150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SPLIT DIRECT MEMORY ACCESS (DMA) [patent_app_type] => utility [patent_app_number] => 17/099896 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099896 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099896
Split direct memory access (DMA) with streaming interconnect Nov 16, 2020 Issued
Array ( [id] => 16713873 [patent_doc_number] => 20210081020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => APPARATUS AND METHOD FOR EFFICIENT ESTIMATION OF THE ENERGY DISSIPATION OF PROCESSOR BASED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/093087 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093087
Energy-efficient global scheduler and scheduling method for managing a plurality of racks Nov 8, 2020 Issued
Array ( [id] => 16659303 [patent_doc_number] => 20210055940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => Efficient Configuration Of A Reconfigurable Data Processor [patent_app_type] => utility [patent_app_number] => 17/093543 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093543
Configuration of a reconfigurable data processor using sub-files Nov 8, 2020 Issued
Array ( [id] => 17907649 [patent_doc_number] => 11461504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio [patent_app_type] => utility [patent_app_number] => 17/087414 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7315 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087414
Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio Nov 1, 2020 Issued
Array ( [id] => 17454934 [patent_doc_number] => 11269795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Intelligent controller and sensor network bus, system and method including a link media expansion and conversion mechanism [patent_app_type] => utility [patent_app_number] => 17/079237 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 43 [patent_no_of_words] => 50140 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079237
Intelligent controller and sensor network bus, system and method including a link media expansion and conversion mechanism Oct 22, 2020 Issued
Array ( [id] => 16623595 [patent_doc_number] => 20210042248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => PARTIAL LINK WIDTH STATES FOR MULTILANE LINKS [patent_app_type] => utility [patent_app_number] => 17/076739 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076739
Technologies for partial link width states for multilane links Oct 20, 2020 Issued
Array ( [id] => 16618153 [patent_doc_number] => 20210036806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => INTELLIGENT CONTROLLER AND SENSOR NETWORK BUS, SYSTEM AND METHOD INCLUDING AN ERROR AVOIDANCE AND CORRECTION MECHANISM [patent_app_type] => utility [patent_app_number] => 17/066915 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -41 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066915
Intelligent controller and sensor network bus, system and method including an error avoidance and correction mechanism Oct 8, 2020 Issued
Array ( [id] => 16615904 [patent_doc_number] => 20210034557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => INTELLIGENT CONTROLLER AND SENSOR NETWORK BUS, SYSTEM AND METHOD INCLUDING A DYNAMIC BANDWIDTH ALLOCATION MECHANISM [patent_app_type] => utility [patent_app_number] => 17/067132 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067132
Intelligent controller and sensor network bus, system and method including a dynamic bandwidth allocation mechanism Oct 8, 2020 Issued
Array ( [id] => 17651529 [patent_doc_number] => 11354258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => Control plane operation at distributed computing system [patent_app_type] => utility [patent_app_number] => 17/038623 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038623
Control plane operation at distributed computing system Sep 29, 2020 Issued
Array ( [id] => 17507145 [patent_doc_number] => 20220100248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => EXPANDED FUNCTION DATAGRAM IN A SYSTEM POWER MANAGEMENT INTERFACE (SPMI) SYSTEM [patent_app_type] => utility [patent_app_number] => 17/037984 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037984
Integrated circuit Sep 29, 2020 Issued
Array ( [id] => 17507581 [patent_doc_number] => 20220100684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => TECHNIQUES USING WORKLOAD CLUSTERING FOR CONFIGURATION RECOMMENDATIONS [patent_app_type] => utility [patent_app_number] => 17/038041 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038041
Techniques for recommending configuration changes using a decision tree Sep 29, 2020 Issued
Array ( [id] => 18981975 [patent_doc_number] => 11907148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => OCP adapter card and computer device [patent_app_type] => utility [patent_app_number] => 17/789365 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17789365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/789365
OCP adapter card and computer device Sep 27, 2020 Issued
Array ( [id] => 16577418 [patent_doc_number] => 20210011819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => TECHNIQUES FOR MANAGING CONTEXT INFORMATION FOR A STORAGE DEVICE WHILE MAINTAINING RESPONSIVENESS [patent_app_type] => utility [patent_app_number] => 17/033420 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033420
Techniques for managing context information for a storage device while maintaining responsiveness Sep 24, 2020 Issued
Array ( [id] => 17083867 [patent_doc_number] => 20210278873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => CLOCK CONTROL SCHEMES FOR A GRAPHICS PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 17/032701 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/032701
Separate clocking for components of a graphics processing unit Sep 24, 2020 Issued
Array ( [id] => 17999691 [patent_doc_number] => 11500799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Managing access to a CPU on behalf of a block application and a non-block application [patent_app_type] => utility [patent_app_number] => 17/029646 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 16827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029646
Managing access to a CPU on behalf of a block application and a non-block application Sep 22, 2020 Issued
Array ( [id] => 17379978 [patent_doc_number] => 11237994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Interrupt controller for controlling interrupts based on priorities of interrupts [patent_app_type] => utility [patent_app_number] => 17/025482 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6821 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025482
Interrupt controller for controlling interrupts based on priorities of interrupts Sep 17, 2020 Issued
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