Search

David B. Thomas

Examiner (ID: 1929, Phone: (571)272-4497 , Office: P/3723 )

Most Active Art Unit
3723
Art Unit(s)
3723
Total Applications
3255
Issued Applications
2639
Pending Applications
134
Abandoned Applications
512

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16095619 [patent_doc_number] => 20200201796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => INTERRUPT MONITORING SYSTEMS AND METHODS FOR FAILURE DETECTION FOR A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/806759 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806759 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806759
Interrupt monitoring systems and methods for failure detection for a semiconductor device Mar 1, 2020 Issued
Array ( [id] => 17924374 [patent_doc_number] => 11467621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness [patent_app_type] => utility [patent_app_number] => 16/804045 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12248 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/804045
Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness Feb 27, 2020 Issued
Array ( [id] => 19370838 [patent_doc_number] => 12062936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Controlling power supply from an electric power source to communication facilities in a communication system [patent_app_type] => utility [patent_app_number] => 17/802000 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11074 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17802000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/802000
Controlling power supply from an electric power source to communication facilities in a communication system Feb 27, 2020 Issued
Array ( [id] => 16551803 [patent_doc_number] => 10884963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Method for integrating a further bus subscriber into a bus system, and bus system for integrating a further bus subscriber therein [patent_app_type] => utility [patent_app_number] => 16/799675 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799675
Method for integrating a further bus subscriber into a bus system, and bus system for integrating a further bus subscriber therein Feb 23, 2020 Issued
Array ( [id] => 16683399 [patent_doc_number] => 10942877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Methods and systems for devices with self-selecting bus decoder [patent_app_type] => utility [patent_app_number] => 16/799444 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799444 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799444
Methods and systems for devices with self-selecting bus decoder Feb 23, 2020 Issued
Array ( [id] => 18104190 [patent_doc_number] => 11544076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Online reconfiguration of a node in a process control system [patent_app_type] => utility [patent_app_number] => 16/799406 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6510 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799406
Online reconfiguration of a node in a process control system Feb 23, 2020 Issued
Array ( [id] => 17039237 [patent_doc_number] => 20210255873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SYSTEMS AND METHODS FOR BINDING SECONDARY OPERATING SYSTEM TO PLATFORM BASIC INPUT/OUTPUT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/793361 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793361
Systems and methods for binding secondary operating system to platform basic input/output system Feb 17, 2020 Issued
Array ( [id] => 16871984 [patent_doc_number] => 20210165451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => USB DOCKING STATION AND POWER-GOVERNING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/793472 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793472
USB docking station with output power adjustment and method thereof Feb 17, 2020 Issued
Array ( [id] => 17151569 [patent_doc_number] => 11144647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => System and method for secure image load boot flow using hashed metadata [patent_app_type] => utility [patent_app_number] => 16/790166 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7311 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/790166
System and method for secure image load boot flow using hashed metadata Feb 12, 2020 Issued
Array ( [id] => 17194906 [patent_doc_number] => 11163662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => System and method for analyzing bus data [patent_app_type] => utility [patent_app_number] => 16/788832 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788832 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788832
System and method for analyzing bus data Feb 11, 2020 Issued
Array ( [id] => 16240369 [patent_doc_number] => 20200257603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => ELECTRONIC ELEMENT, SYSTEM COMPRISING SUCH AN ELECTRONIC ELEMENT AND METHOD FOR MONITORING A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/787335 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787335
Electronic element, system comprising such an electronic element and method for monitoring and cutting off a processor on occurrence of a failure event Feb 10, 2020 Issued
Array ( [id] => 16514633 [patent_doc_number] => 20200393891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => PHYSICAL LAYER DEVICE WITH SLEEP MODE AND PARTIAL NETWORKING SUPPORT AND RELATED SYSTEMS, METHODS AND DEVICES [patent_app_type] => utility [patent_app_number] => 16/781227 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781227 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781227
Managing power at a station via a physical layer device and related systems, methods and devices Feb 3, 2020 Issued
Array ( [id] => 15998177 [patent_doc_number] => 20200174959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => METHODS AND APPARATUS FOR PROGRAMMING AN INTEGRATED CIRCUIT USING A CONFIGURATION MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 16/780713 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780713
Methods and apparatus for programming an integrated circuit using a configuration memory module Feb 2, 2020 Issued
Array ( [id] => 17136587 [patent_doc_number] => 11138140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Configuring first subsystem with a master processor and a second subsystem with a slave processor [patent_app_type] => utility [patent_app_number] => 16/779184 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10569 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16779184 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/779184
Configuring first subsystem with a master processor and a second subsystem with a slave processor Jan 30, 2020 Issued
Array ( [id] => 17106008 [patent_doc_number] => 11126220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => System and method for time synchronization between information handling systems [patent_app_type] => utility [patent_app_number] => 16/775963 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6914 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16775963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/775963
System and method for time synchronization between information handling systems Jan 28, 2020 Issued
Array ( [id] => 18046648 [patent_doc_number] => 11520602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Generating configuration corrections for applications using a classifier model [patent_app_type] => utility [patent_app_number] => 16/773554 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/773554
Generating configuration corrections for applications using a classifier model Jan 26, 2020 Issued
Array ( [id] => 16209081 [patent_doc_number] => 20200242071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SERIAL BUS SIGNAL CONDITIONER [patent_app_type] => utility [patent_app_number] => 16/751411 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/751411
Serial bus signal conditioner Jan 23, 2020 Issued
Array ( [id] => 17209192 [patent_doc_number] => 11169561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Clock data recovery device and method to alternatively adjust phases of outputted clock signals [patent_app_type] => utility [patent_app_number] => 16/748805 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6123 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748805
Clock data recovery device and method to alternatively adjust phases of outputted clock signals Jan 21, 2020 Issued
Array ( [id] => 16906107 [patent_doc_number] => 20210185023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => PARALLEL SCHEDULING OF ENCRYPTION ENGINES AND DECRYPTION ENGINES TO PREVENT SIDE CHANNEL ATTACKS [patent_app_type] => utility [patent_app_number] => 16/749250 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16749250 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/749250
Parallel scheduling of encryption engines and decryption engines to prevent side channel attacks Jan 21, 2020 Issued
Array ( [id] => 16208894 [patent_doc_number] => 20200241884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => METHOD AND CONTROL TERMINAL FOR CONFIGURING BASIC INPUT/OUTPUT SYSTEM SETTINGS OF A COMPUTER [patent_app_type] => utility [patent_app_number] => 16/747252 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747252
Method and control terminal for configuring basic input/output system settings of a computer Jan 19, 2020 Issued
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