Search

David B. Thomas

Examiner (ID: 1929, Phone: (571)272-4497 , Office: P/3723 )

Most Active Art Unit
3723
Art Unit(s)
3723
Total Applications
3255
Issued Applications
2639
Pending Applications
134
Abandoned Applications
512

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16145037 [patent_doc_number] => 10705588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Enabling a non-core domain to control memory bandwidth in a processor [patent_app_type] => utility [patent_app_number] => 16/249103 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249103
Enabling a non-core domain to control memory bandwidth in a processor Jan 15, 2019 Issued
Array ( [id] => 15545267 [patent_doc_number] => 10572414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Methods and systems for devices with self-selecting bus decoder [patent_app_type] => utility [patent_app_number] => 16/247244 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9343 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247244
Methods and systems for devices with self-selecting bus decoder Jan 13, 2019 Issued
Array ( [id] => 15425929 [patent_doc_number] => 10545893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-28 [patent_title] => Interrupt controller and method of operation of an interrupt controller [patent_app_type] => utility [patent_app_number] => 16/245337 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10888 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16245337 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/245337
Interrupt controller and method of operation of an interrupt controller Jan 10, 2019 Issued
Array ( [id] => 14570339 [patent_doc_number] => 20190212776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/244308 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244308 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/244308
Electronic apparatus with multiple operating systems and control method thereof Jan 9, 2019 Issued
Array ( [id] => 16065113 [patent_doc_number] => 10691506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Distributed lock for data acquisition systems [patent_app_type] => utility [patent_app_number] => 16/236162 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236162 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236162
Distributed lock for data acquisition systems Dec 27, 2018 Issued
Array ( [id] => 16216892 [patent_doc_number] => 10732700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Self-timed clocked processor architecture [patent_app_type] => utility [patent_app_number] => 16/233946 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/233946
Self-timed clocked processor architecture Dec 26, 2018 Issued
Array ( [id] => 15593797 [patent_doc_number] => 20200073433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => METHOD OF CLOCK GATE ANALYSIS OF ELECTRONIC SYSTEM DESIGNS AND RELATED SYSTEMS, METHODS AND DEVICES [patent_app_type] => utility [patent_app_number] => 16/228445 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228445
Method of clock gate analysis for improved efficiency of electronic circuitry system designs and related systems, methods and devices Dec 19, 2018 Issued
Array ( [id] => 16666793 [patent_doc_number] => 10936036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Soft-start switch circuits using separated power supply paths and related methods and systems [patent_app_type] => utility [patent_app_number] => 16/224610 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16224610 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/224610
Soft-start switch circuits using separated power supply paths and related methods and systems Dec 17, 2018 Issued
Array ( [id] => 15887201 [patent_doc_number] => 10649945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-12 [patent_title] => Non-native digital interface support over a two-wire communication bus [patent_app_type] => utility [patent_app_number] => 16/215566 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 19216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215566
Non-native digital interface support over a two-wire communication bus Dec 9, 2018 Issued
Array ( [id] => 14161737 [patent_doc_number] => 20190107971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => SYSTEM AND METHOD FOR PROVIDING INPUT/OUTPUT DETERMINISM [patent_app_type] => utility [patent_app_number] => 16/214817 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214817
System and method for providing input/output determinism based on required execution time Dec 9, 2018 Issued
Array ( [id] => 14165341 [patent_doc_number] => 20190109773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => INFERRING PHYSICAL LAYER CONNECTION STATUS OF GENERIC CABLES FROM PLANNED SINGLE-END CONNECTION EVENTS [patent_app_type] => utility [patent_app_number] => 16/210141 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210141
Inferring physical layer connection status of generic cables from planned single-end connection events Dec 4, 2018 Issued
Array ( [id] => 15966467 [patent_doc_number] => 20200166985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => MULTI-TIERED LOW POWER STATES [patent_app_type] => utility [patent_app_number] => 16/210985 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210985
Multi-tiered low power states Dec 4, 2018 Issued
Array ( [id] => 16637123 [patent_doc_number] => 10915633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Method and apparatus for device security verification utilizing a virtual trusted computing base [patent_app_type] => utility [patent_app_number] => 16/204802 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204802
Method and apparatus for device security verification utilizing a virtual trusted computing base Nov 28, 2018 Issued
Array ( [id] => 15935821 [patent_doc_number] => 20200159544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => CONFIGURATION LOAD OF A RECONFIGURABLE DATA PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/197826 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197826
Configuration load of a reconfigurable data processor Nov 20, 2018 Issued
Array ( [id] => 15903201 [patent_doc_number] => 20200151120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => STREAMING PLATFORM ARCHITECTURE FOR INTER-KERNEL CIRCUIT COMMUNICATION FOR AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/186055 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186055 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186055
Streaming platform architecture for inter-kernel circuit communication for an integrated circuit Nov 8, 2018 Issued
Array ( [id] => 15328763 [patent_doc_number] => 20200004711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHOD AND DEVICE FOR PROCESSING DATA BASED ON DISTRIBUTED STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/186415 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186415
Method and device for processing network data traffic based on distributed structure Nov 8, 2018 Issued
Array ( [id] => 15908469 [patent_doc_number] => 20200153756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => STREAMING PLATFORM FLOW AND ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/186102 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186102
Streaming platform flow and architecture for an integrated circuit Nov 8, 2018 Issued
Array ( [id] => 14022401 [patent_doc_number] => 20190073194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => SCALABLE INPUT/OUTPUT SYSTEM AND TECHNIQUES TO TRANSMIT DATA BETWEEN DOMAINS WITHOUT A CENTRAL PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/182932 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182932
Scalable input/output system and techniques to transmit data between domains without a central processor Nov 6, 2018 Issued
Array ( [id] => 15789271 [patent_doc_number] => 10628360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Data processor using a ring bus and method for controlling the same [patent_app_type] => utility [patent_app_number] => 16/178302 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12210 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16178302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/178302
Data processor using a ring bus and method for controlling the same Oct 31, 2018 Issued
Array ( [id] => 16216410 [patent_doc_number] => 10732212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Impedance isolated lower voltage and wired data communication network [patent_app_type] => utility [patent_app_number] => 16/176937 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 12382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176937
Impedance isolated lower voltage and wired data communication network Oct 30, 2018 Issued
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