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David B. Thomas

Examiner (ID: 1929, Phone: (571)272-4497 , Office: P/3723 )

Most Active Art Unit
3723
Art Unit(s)
3723
Total Applications
3255
Issued Applications
2639
Pending Applications
134
Abandoned Applications
512

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20395050 [patent_doc_number] => 20250370525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => VERIFICATION OF POWER CABLE CHECK ON SERVER EQUIPMENT [patent_app_type] => utility [patent_app_number] => 18/675219 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675219
VERIFICATION OF POWER CABLE CHECK ON SERVER EQUIPMENT May 27, 2024 Pending
Array ( [id] => 19434387 [patent_doc_number] => 20240302885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => PATTERN-BASED ACTIVATION OF MEMORY POWER CONSUMPTION MODE [patent_app_type] => utility [patent_app_number] => 18/667548 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667548 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667548
Activation of memory power consumption mode based on pattern of power state change requests May 16, 2024 Issued
Array ( [id] => 20365670 [patent_doc_number] => 20250355482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => Method of Minimizing Rusting at a Power Interface of a Wearable Computing Device [patent_app_type] => utility [patent_app_number] => 18/663310 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663310
Method of minimizing rusting at a power interface of a wearable computing device May 13, 2024 Issued
Array ( [id] => 20351596 [patent_doc_number] => 20250348448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => DERIVING SYSTEM CLOCK FROM GATED DATA CLOCK [patent_app_type] => utility [patent_app_number] => 18/662974 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662974
DERIVING SYSTEM CLOCK FROM GATED DATA CLOCK May 12, 2024 Pending
Array ( [id] => 19588088 [patent_doc_number] => 20240385645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => LATENCY SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 18/659991 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659991
LATENCY SYNCHRONIZATION May 8, 2024 Pending
Array ( [id] => 19405779 [patent_doc_number] => 20240289290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SECURE ENCLAVE SYSTEM-IN-PACKAGE [patent_app_type] => utility [patent_app_number] => 18/655486 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655486
Secure enclave system-in-package May 5, 2024 Issued
Array ( [id] => 20323180 [patent_doc_number] => 20250335268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => DYNAMIC OPTIMIZATION OF POWER CONSUMPTION IN STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/649113 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649113
DYNAMIC OPTIMIZATION OF POWER CONSUMPTION IN STORAGE SYSTEMS Apr 28, 2024 Pending
Array ( [id] => 20322907 [patent_doc_number] => 20250334995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => Low Latency Gearbox Retimer Architecture [patent_app_type] => utility [patent_app_number] => 18/649933 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649933
Low latency gearbox retimer architecture Apr 28, 2024 Issued
Array ( [id] => 20537595 [patent_doc_number] => 12554672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Link layer-PHY interface adapter [patent_app_type] => utility [patent_app_number] => 18/648122 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 19414 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648122
Link layer-PHY interface adapter Apr 25, 2024 Issued
Array ( [id] => 20322911 [patent_doc_number] => 20250334999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => CLOCK SYNCHRONIZATION IN A MULTICHIP MODULE [patent_app_type] => utility [patent_app_number] => 18/644595 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644595
CLOCK SYNCHRONIZATION IN A MULTICHIP MODULE Apr 23, 2024 Pending
Array ( [id] => 20689145 [patent_doc_number] => 12619294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => System and method for controlling an appliance with a loss of power [patent_app_type] => utility [patent_app_number] => 18/644806 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2318 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644806
System and method for controlling an appliance with a loss of power Apr 23, 2024 Issued
Array ( [id] => 20442175 [patent_doc_number] => 12513017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Wire fault detection techniques for power over communications cabling [patent_app_type] => utility [patent_app_number] => 18/642981 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642981
Wire fault detection techniques for power over communications cabling Apr 22, 2024 Issued
Array ( [id] => 20296369 [patent_doc_number] => 20250321612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => TIME SYNCHRONIZATION BETWEEN CHASSIS COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/634572 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634572
TIME SYNCHRONIZATION BETWEEN CHASSIS COMPONENTS Apr 11, 2024 Pending
Array ( [id] => 19516387 [patent_doc_number] => 20240348073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => ELECTRONIC APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/625524 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625524
Electronic apparatus, control method, and storage medium Apr 2, 2024 Issued
Array ( [id] => 20284405 [patent_doc_number] => 20250309647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR IMPROVING POWER MANAGEMENT IN PROCESSORS VIA ARTIFICIAL NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 18/617501 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617501 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617501
APPARATUSES, SYSTEMS, AND METHODS FOR IMPROVING POWER MANAGEMENT IN PROCESSORS VIA ARTIFICIAL NEURAL NETWORKS Mar 25, 2024 Pending
Array ( [id] => 19513931 [patent_doc_number] => 20240345617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEPARATE CLOCKING FOR COMPONENTS OF A GRAPHICS PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/603883 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603883
Workload-based clocking for circuitry components Mar 12, 2024 Issued
Array ( [id] => 19711356 [patent_doc_number] => 20250021498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => AREA EFFICIENT ASYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) BUFFER FOR HIGH BANDWIDTH DATA TRANSFER USING EVENT TRANSFER BLOCKS [patent_app_type] => utility [patent_app_number] => 18/601341 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601341
AREA EFFICIENT ASYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) BUFFER FOR HIGH BANDWIDTH DATA TRANSFER USING EVENT TRANSFER BLOCKS Mar 10, 2024 Pending
Array ( [id] => 20195400 [patent_doc_number] => 20250272110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => EXECUTION OF CONFIGURATION FILES GENERATED FROM SPECIFICATION FILES [patent_app_type] => utility [patent_app_number] => 18/587029 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587029
EXECUTION OF CONFIGURATION FILES GENERATED FROM SPECIFICATION FILES Feb 25, 2024 Pending
Array ( [id] => 19971184 [patent_doc_number] => 12339795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Circuit device with multiple parallel data paths [patent_app_type] => utility [patent_app_number] => 18/581522 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581522
Circuit device with multiple parallel data paths Feb 19, 2024 Issued
Array ( [id] => 19391481 [patent_doc_number] => 20240281351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => POWER SAVING BY LOADING REPAIR INFORMATION BEFORE MEMORY DEVICE SENSING [patent_app_type] => utility [patent_app_number] => 18/442704 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442704 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442704
POWER SAVING BY LOADING REPAIR INFORMATION BEFORE MEMORY DEVICE SENSING Feb 14, 2024 Pending
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