Search

David Bochna

Examiner (ID: 2452, Phone: (571)272-7078 , Office: P/3679 )

Most Active Art Unit
3679
Art Unit(s)
3629, 3626, 3679
Total Applications
2864
Issued Applications
2187
Pending Applications
160
Abandoned Applications
514

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16210398 [patent_doc_number] => 20200243388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => BACKSIDE METAL REMOVAL DIE SINGULATION SYSTEMS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/505632 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505632 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505632
Backside metal removal die singulation systems and related methods Jul 7, 2019 Issued
Array ( [id] => 16545250 [patent_doc_number] => 20200411665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING VERTICAL TRANSISTOR WITH SAGE GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/454398 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16454398 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/454398
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING VERTICAL TRANSISTOR WITH SAGE GATE STRUCTURE Jun 26, 2019 Abandoned
Array ( [id] => 15299231 [patent_doc_number] => 20190392751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => DISPLAY APPARATUS WITH ARRAY OF LIGHT EMITTING DIODES AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/447484 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447484 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447484
Display apparatus with array of light emitting diodes and method of manufacturing the same Jun 19, 2019 Issued
Array ( [id] => 15218289 [patent_doc_number] => 20190371831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => VEHICLE, DISPLAY DEVICE AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/444522 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444522 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444522
Vehicle, display device and manufacturing method for a semiconductor device Jun 17, 2019 Issued
Array ( [id] => 15519833 [patent_doc_number] => 10566515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Extended area of sputter deposited N-type and P-type thermoelectric legs in a flexible thin-film based thermoelectric device [patent_app_type] => utility [patent_app_number] => 16/440963 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/440963
Extended area of sputter deposited N-type and P-type thermoelectric legs in a flexible thin-film based thermoelectric device Jun 12, 2019 Issued
Array ( [id] => 14894881 [patent_doc_number] => 20190291206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => MITIGATION OF PARTICLE CONTAMINATION FOR WAFER DICING PROCESSES [patent_app_type] => utility [patent_app_number] => 16/439553 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439553 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/439553
Mitigation of particle contamination for wafer dicing processes Jun 11, 2019 Issued
Array ( [id] => 14843597 [patent_doc_number] => 20190280199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/426475 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/426475
Electronic device and method for fabricating the same May 29, 2019 Issued
Array ( [id] => 15250039 [patent_doc_number] => 10510548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/422006 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 8805 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422006
Semiconductor structure May 23, 2019 Issued
Array ( [id] => 14839455 [patent_doc_number] => 20190278128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => METHODS OF MANUFACTURING DISPLAY PANELS AND DISPLAY PANELS [patent_app_type] => utility [patent_app_number] => 16/420196 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420196
Methods of manufacturing display panels and display panels May 22, 2019 Issued
Array ( [id] => 14813133 [patent_doc_number] => 20190273176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => TILED SOLAR CELL LASER PROCESS [patent_app_type] => utility [patent_app_number] => 16/418859 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418859 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/418859
Tiled solar cell laser process May 20, 2019 Issued
Array ( [id] => 15300357 [patent_doc_number] => 20190393314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => Vertical Transistor Device Structure with Cylindrical-Shaped Field Plates [patent_app_type] => utility [patent_app_number] => 16/410773 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410773
Vertical Transistor Device Structure with Cylindrical-Shaped Field Plates May 12, 2019 Abandoned
Array ( [id] => 16417712 [patent_doc_number] => 10825612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Tunable coplanar capacitor with vertical tuning and lateral RF path and methods for manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/409188 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409188 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409188
Tunable coplanar capacitor with vertical tuning and lateral RF path and methods for manufacturing thereof May 9, 2019 Issued
Array ( [id] => 14815227 [patent_doc_number] => 20190274223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => CIRCUIT BOARD AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 16/408772 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408772 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408772
Circuit board and method of forming same May 9, 2019 Issued
Array ( [id] => 16609254 [patent_doc_number] => 10910268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Method of manufacturing a chip package [patent_app_type] => utility [patent_app_number] => 16/403626 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3617 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/403626
Method of manufacturing a chip package May 5, 2019 Issued
Array ( [id] => 16803236 [patent_doc_number] => 10998188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Gallium nitride laminated substrate and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/403859 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6987 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403859 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/403859
Gallium nitride laminated substrate and semiconductor device May 5, 2019 Issued
Array ( [id] => 15791467 [patent_doc_number] => 10629465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Method for calibrating a component mounting apparatus [patent_app_type] => utility [patent_app_number] => 16/403533 [patent_app_country] => US [patent_app_date] => 2019-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4962 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 418 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/403533
Method for calibrating a component mounting apparatus May 3, 2019 Issued
Array ( [id] => 16668498 [patent_doc_number] => 10937756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same [patent_app_type] => utility [patent_app_number] => 16/402747 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2987 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402747
Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same May 2, 2019 Issued
Array ( [id] => 14753295 [patent_doc_number] => 20190259821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => LIGHT EMITTING DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/401406 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/401406
Light emitting display apparatus May 1, 2019 Issued
Array ( [id] => 14753061 [patent_doc_number] => 20190259704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => RING-IN-RING CONFIGURABLE-CAPACITANCE STIFFENERS AND METHODS OF ASSEMBLING SAME [patent_app_type] => utility [patent_app_number] => 16/401661 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401661 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/401661
Ring-in-ring configurable-capacitance stiffeners and methods of assembling same May 1, 2019 Issued
Array ( [id] => 16645791 [patent_doc_number] => 10923659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Wafers for use in aligning nanotubes and methods of making and using the same [patent_app_type] => utility [patent_app_number] => 16/401042 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 50 [patent_no_of_words] => 8309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/401042
Wafers for use in aligning nanotubes and methods of making and using the same Apr 30, 2019 Issued
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