David Browe

Array ( [id] => 2761790 [patent_doc_number] => 04994402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-19 [patent_title] => 'Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/400609 [patent_app_country] => US [patent_app_date] => 1989-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 4580 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/994/04994402.pdf [firstpage_image] =>[orig_patent_app_number] => 400609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2628386 [patent_doc_number] => 04916087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-10 [patent_title] => 'Method of manufacturing a semiconductor device by filling and planarizing narrow and wide trenches' [patent_app_type] => 1 [patent_app_number] => 7/400013 [patent_app_country] => US [patent_app_date] => 1989-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 3215 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/916/04916087.pdf [firstpage_image] =>[orig_patent_app_number] => 400013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2635972 [patent_doc_number] => 04910157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-20 [patent_title] => 'Method of producing recessed gate of MESFET in compound semiconductor' [patent_app_type] => 1 [patent_app_number] => 7/397886 [patent_app_country] => US [patent_app_date] => 1989-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 2090 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/910/04910157.pdf [firstpage_image] =>[orig_patent_app_number] => 397886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2558354 [patent_doc_number] => 04942137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-17 [patent_title] => 'Self-aligned trench with selective trench fill' [patent_app_type] => 1 [patent_app_number] => 7/393210 [patent_app_country] => US [patent_app_date] => 1989-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3797 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/942/04942137.pdf [firstpage_image] =>[orig_patent_app_number] => 393210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2875667 [patent_doc_number] => 05118631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Self-aligned antiblooming structure for charge-coupled devices and method of fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 7/390429 [patent_app_country] => US [patent_app_date] => 1989-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 3496 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/118/05118631.pdf [firstpage_image] =>[orig_patent_app_number] => 390429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2595371 [patent_doc_number] => 04923826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-08 [patent_title] => 'Method for forming dielectrically isolated transistor' [patent_app_type] => 1 [patent_app_number] => 7/388416 [patent_app_country] => US [patent_app_date] => 1989-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2538 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/923/04923826.pdf [firstpage_image] =>[orig_patent_app_number] => 388416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2561751 [patent_doc_number] => 04900373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-13 [patent_title] => 'Sensitization pretreatment of Pb-salt epitaxial films for schottky diodes by sulfur vapor exposure' [patent_app_type] => 1 [patent_app_number] => 7/381880 [patent_app_country] => US [patent_app_date] => 1989-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3769 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/900/04900373.pdf [firstpage_image] =>[orig_patent_app_number] => 381880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2668813 [patent_doc_number] => 05034338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Circuit containing integrated bipolar and complementary MOS transistors on a common substrate' [patent_app_type] => 1 [patent_app_number] => 7/379108 [patent_app_country] => US [patent_app_date] => 1989-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1817 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034338.pdf [firstpage_image] =>[orig_patent_app_number] => 379108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2472874 [patent_doc_number] => 04886762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-12 [patent_title] => 'Monolithic temperature compensated voltage-reference diode and method for its manufacture' [patent_app_type] => 1 [patent_app_number] => 7/375236 [patent_app_country] => US [patent_app_date] => 1989-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2222 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/886/04886762.pdf [firstpage_image] =>[orig_patent_app_number] => 375236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2586415 [patent_doc_number] => 04908331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-13 [patent_title] => 'Method of manufacturing a semiconductor device by depositing metal on semiconductor maintained at temperature to form silicide' [patent_app_type] => 1 [patent_app_number] => 7/369443 [patent_app_country] => US [patent_app_date] => 1989-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2357 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/908/04908331.pdf [firstpage_image] =>[orig_patent_app_number] => 369443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2706431 [patent_doc_number] => 04981829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Oxidative conversion of methane to ethylene and ethane' [patent_app_type] => 1 [patent_app_number] => 7/366654 [patent_app_country] => US [patent_app_date] => 1989-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3798 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/981/04981829.pdf [firstpage_image] =>[orig_patent_app_number] => 366654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2587667 [patent_doc_number] => 04927773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-22 [patent_title] => 'Method of minimizing implant-related damage to a group II-VI semiconductor material' [patent_app_type] => 1 [patent_app_number] => 7/361452 [patent_app_country] => US [patent_app_date] => 1989-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2511 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/927/04927773.pdf [firstpage_image] =>[orig_patent_app_number] => 361452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2632249 [patent_doc_number] => 04952524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Semiconductor device manufacture including trench formation' [patent_app_type] => 1 [patent_app_number] => 7/347975 [patent_app_country] => US [patent_app_date] => 1989-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3737 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/952/04952524.pdf [firstpage_image] =>[orig_patent_app_number] => 347975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742383 [patent_doc_number] => 05028564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Edge doping processes for mesa structures in SOS and SOI devices' [patent_app_type] => 1 [patent_app_number] => 7/352583 [patent_app_country] => US [patent_app_date] => 1989-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 1988 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028564.pdf [firstpage_image] =>[orig_patent_app_number] => 352583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2555335 [patent_doc_number] => 04897363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-30 [patent_title] => 'Method of manufacturing semiconductor device isolation' [patent_app_type] => 1 [patent_app_number] => 7/342086 [patent_app_country] => US [patent_app_date] => 1989-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 3635 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/897/04897363.pdf [firstpage_image] =>[orig_patent_app_number] => 342086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2567676 [patent_doc_number] => 04900692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-13 [patent_title] => 'Method of forming an oxide liner and active area mask for selective epitaxial growth in an isolation trench' [patent_app_type] => 1 [patent_app_number] => 7/342156 [patent_app_country] => US [patent_app_date] => 1989-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1620 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/900/04900692.pdf [firstpage_image] =>[orig_patent_app_number] => 342156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2584732 [patent_doc_number] => 04925805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'Method of manufacturing a semiconductor device having an SOI structure using selectable etching' [patent_app_type] => 1 [patent_app_number] => 7/333062 [patent_app_country] => US [patent_app_date] => 1989-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/925/04925805.pdf [firstpage_image] =>[orig_patent_app_number] => 333062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2567604 [patent_doc_number] => 04900688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-13 [patent_title] => 'Pseudo uniphase charge coupled device fabrication by self-aligned virtual barrier and virtual gate formation' [patent_app_type] => 1 [patent_app_number] => 7/332856 [patent_app_country] => US [patent_app_date] => 1989-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5825 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/900/04900688.pdf [firstpage_image] =>[orig_patent_app_number] => 332856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2632232 [patent_doc_number] => 04952523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Process for fabricating charge-coupled device with reduced surface state at semiconductor-insulator interface' [patent_app_type] => 1 [patent_app_number] => 7/331701 [patent_app_country] => US [patent_app_date] => 1989-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6330 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/952/04952523.pdf [firstpage_image] =>[orig_patent_app_number] => 331701 [rel_patent_id] =>[rel_patent_doc_number] =>)