Search

David C. Mis

Examiner (ID: 13742)

Most Active Art Unit
2817
Art Unit(s)
2817, 2502, 2504
Total Applications
3251
Issued Applications
3048
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5531264 [patent_doc_number] => 20090231052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'PULSE WIDTH MODULATION STRUCTURE ENABLING REGULATED DUTY CYCLE' [patent_app_type] => utility [patent_app_number] => 12/047881 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2751 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231052.pdf [firstpage_image] =>[orig_patent_app_number] => 12047881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047881
Pulse width modulation structure enabling regulated duty cycle Mar 12, 2008 Issued
Array ( [id] => 5531260 [patent_doc_number] => 20090231048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'BIAS CIRCUIT TO STABILIZE OSCILLATION IN RING OSCILLATOR, OSCILLATOR, AND METHOD TO STABILIZE OSCILLATION IN RING OSCILLATOR' [patent_app_type] => utility [patent_app_number] => 12/073958 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5346 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231048.pdf [firstpage_image] =>[orig_patent_app_number] => 12073958 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073958
Bias circuit to stabilize oscillation in ring oscillator, oscillator, and method to stabilize oscillation in ring oscillator Mar 11, 2008 Issued
Array ( [id] => 5531265 [patent_doc_number] => 20090231053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Modulator' [patent_app_type] => utility [patent_app_number] => 12/075364 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4981 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231053.pdf [firstpage_image] =>[orig_patent_app_number] => 12075364 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/075364
Modulator Mar 10, 2008 Issued
Array ( [id] => 342161 [patent_doc_number] => 07501919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Boosted-bias tunable filter with dynamic calibration' [patent_app_type] => utility [patent_app_number] => 12/043662 [patent_app_country] => US [patent_app_date] => 2008-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 6774 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501919.pdf [firstpage_image] =>[orig_patent_app_number] => 12043662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/043662
Boosted-bias tunable filter with dynamic calibration Mar 5, 2008 Issued
Array ( [id] => 54543 [patent_doc_number] => 07772935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Oscillator voltage source circuits' [patent_app_type] => utility [patent_app_number] => 12/043713 [patent_app_country] => US [patent_app_date] => 2008-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1612 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772935.pdf [firstpage_image] =>[orig_patent_app_number] => 12043713 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/043713
Oscillator voltage source circuits Mar 5, 2008 Issued
Array ( [id] => 5328474 [patent_doc_number] => 20090108951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'METHODS AND APPARATUS FOR REDUCING PEAK-TO-RMS AMPLITUDE RATIO IN COMMUNICATION SIGNALS' [patent_app_type] => utility [patent_app_number] => 12/042689 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108951.pdf [firstpage_image] =>[orig_patent_app_number] => 12042689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042689
Methods and apparatus for reducing peak-to-RMS amplitude ratio in communication signals Mar 4, 2008 Issued
Array ( [id] => 5383595 [patent_doc_number] => 20090224839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'LOCK LOOP CIRCUIT AND METHOD HAVING IMPROVED LOCK TIME' [patent_app_type] => utility [patent_app_number] => 12/042228 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20090224839.pdf [firstpage_image] =>[orig_patent_app_number] => 12042228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042228
Look loop circuit and method having improved lock time Mar 3, 2008 Issued
Array ( [id] => 170037 [patent_doc_number] => 07667545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Automatic calibration lock loop circuit and method having improved lock time' [patent_app_type] => utility [patent_app_number] => 12/042216 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4864 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/667/07667545.pdf [firstpage_image] =>[orig_patent_app_number] => 12042216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042216
Automatic calibration lock loop circuit and method having improved lock time Mar 3, 2008 Issued
Array ( [id] => 4601274 [patent_doc_number] => 07978111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'High resolution time-to-digital converter' [patent_app_type] => utility [patent_app_number] => 12/041426 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978111.pdf [firstpage_image] =>[orig_patent_app_number] => 12041426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041426
High resolution time-to-digital converter Mar 2, 2008 Issued
Array ( [id] => 217705 [patent_doc_number] => 07612617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Voltage-controlled oscillator gain calibration for two-point modulation in a phase-locked loop' [patent_app_type] => utility [patent_app_number] => 12/040875 [patent_app_country] => US [patent_app_date] => 2008-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/612/07612617.pdf [firstpage_image] =>[orig_patent_app_number] => 12040875 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/040875
Voltage-controlled oscillator gain calibration for two-point modulation in a phase-locked loop Feb 29, 2008 Issued
Array ( [id] => 7599295 [patent_doc_number] => 07583153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-01 [patent_title] => 'Systems and methods for multiplexing multiphase clocks' [patent_app_type] => utility [patent_app_number] => 12/039009 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/583/07583153.pdf [firstpage_image] =>[orig_patent_app_number] => 12039009 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039009
Systems and methods for multiplexing multiphase clocks Feb 27, 2008 Issued
Array ( [id] => 5537294 [patent_doc_number] => 20090219099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'DIGITAL SYNTHESIZER FOR LOW POWER LOCATION RECEIVERS' [patent_app_type] => utility [patent_app_number] => 12/039671 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4477 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20090219099.pdf [firstpage_image] =>[orig_patent_app_number] => 12039671 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039671
Digital synthesizer for low power location receivers Feb 27, 2008 Issued
Array ( [id] => 6419989 [patent_doc_number] => 20100277234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'Low Power BPSK Demodulator' [patent_app_type] => utility [patent_app_number] => 12/528967 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5318 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277234.pdf [firstpage_image] =>[orig_patent_app_number] => 12528967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/528967
Low power BPSK demodulator Feb 26, 2008 Issued
Array ( [id] => 4877262 [patent_doc_number] => 20080150645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Discrete Clock Generator and Timing/Frequency Reference' [patent_app_type] => utility [patent_app_number] => 12/036165 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 42931 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150645.pdf [firstpage_image] =>[orig_patent_app_number] => 12036165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036165
Discrete clock generator and timing/frequency reference Feb 21, 2008 Issued
Array ( [id] => 4864395 [patent_doc_number] => 20080143454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Integrated Clock Generator and Timing/Frequency Reference' [patent_app_type] => utility [patent_app_number] => 12/036185 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 38489 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20080143454.pdf [firstpage_image] =>[orig_patent_app_number] => 12036185 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036185
Integrated clock generator and timing/frequency reference Feb 21, 2008 Issued
Array ( [id] => 7788357 [patent_doc_number] => 20120049913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'VOLTAGE-CONTROLLED OSCILLATOR AND GAIN CALIBRATION TECHNIQUE FOR TWO-POINT MODULATION IN A PHASE-LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/035296 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5428 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20120049913.pdf [firstpage_image] =>[orig_patent_app_number] => 12035296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035296
Voltage-controlled oscillator and gain calibration technique for two-point modulation in a phase-locked loop Feb 20, 2008 Issued
Array ( [id] => 229404 [patent_doc_number] => 07602219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Inverting cell' [patent_app_type] => utility [patent_app_number] => 12/034298 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2362 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602219.pdf [firstpage_image] =>[orig_patent_app_number] => 12034298 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034298
Inverting cell Feb 19, 2008 Issued
Array ( [id] => 5390913 [patent_doc_number] => 20090208226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Bang-bang architecture' [patent_app_type] => utility [patent_app_number] => 12/070440 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3642 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20090208226.pdf [firstpage_image] =>[orig_patent_app_number] => 12070440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/070440
Bang-bang architecture Feb 18, 2008 Issued
Array ( [id] => 163695 [patent_doc_number] => 07671688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Reference-less clock circuit' [patent_app_type] => utility [patent_app_number] => 12/032407 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3097 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/671/07671688.pdf [firstpage_image] =>[orig_patent_app_number] => 12032407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032407
Reference-less clock circuit Feb 14, 2008 Issued
Array ( [id] => 4871185 [patent_doc_number] => 20080197919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'FULLY DIFFERENTIAL DEMODULATOR WITH VARIABLE GAIN, AND METHOD FOR DEMODULATING A SIGNAL' [patent_app_type] => utility [patent_app_number] => 12/032481 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4865 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197919.pdf [firstpage_image] =>[orig_patent_app_number] => 12032481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032481
Fully differential demodulator with variable gain, and method for demodulating a signal Feb 14, 2008 Issued
Menu