Search

David C. Spalla

Examiner (ID: 16867)

Most Active Art Unit
2896
Art Unit(s)
2896, 2818, 2821, 2815, 2893, 4148
Total Applications
1049
Issued Applications
860
Pending Applications
66
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19468153 [patent_doc_number] => 20240321823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/531883 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/531883
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Dec 6, 2023 Pending
Array ( [id] => 19239402 [patent_doc_number] => 20240196598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/527470 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527470
SEMICONDUCTOR DEVICE Dec 3, 2023 Pending
Array ( [id] => 20177459 [patent_doc_number] => 12396224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 18/527453 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 8736 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527453 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527453
Integrated circuit device Dec 3, 2023 Issued
Array ( [id] => 19054926 [patent_doc_number] => 20240096895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => UNIFORM GATE WIDTH FOR NANOSTRUCTURE DEVICES [patent_app_type] => utility [patent_app_number] => 18/522687 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522687
Uniform gate width for nanostructure devices Nov 28, 2023 Issued
Array ( [id] => 19900333 [patent_doc_number] => 12278273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device with backside gate isolation structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/520730 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 9093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520730
Semiconductor device with backside gate isolation structure and method for forming the same Nov 27, 2023 Issued
Array ( [id] => 20293202 [patent_doc_number] => 20250318445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => Tunable Josephson Junction with Added Dopants [patent_app_type] => utility [patent_app_number] => 18/518349 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518349
Tunable Josephson Junction with Added Dopants Nov 21, 2023 Pending
Array ( [id] => 20028481 [patent_doc_number] => 20250166703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE INCLUDING CRACK-RESISTANT BACKSIDE PASSIVATION STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/516064 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516064
Three-dimensional memory device including crack-resistant backside passivation structure and methods of forming the same Nov 20, 2023 Issued
Array ( [id] => 19038479 [patent_doc_number] => 20240088294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/515908 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515908
Method of manufacturing a semiconductor device and a semiconductor device Nov 20, 2023 Issued
Array ( [id] => 19468010 [patent_doc_number] => 20240321680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR DEVICE WITH 2-PHASE COOLING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/514514 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514514
SEMICONDUCTOR DEVICE WITH 2-PHASE COOLING STRUCTURE Nov 19, 2023 Pending
Array ( [id] => 19038438 [patent_doc_number] => 20240088253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBON CHANNEL STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/510402 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510402
Gate-all-around integrated circuit structures having dual nanoribbon channel structures Nov 14, 2023 Issued
Array ( [id] => 20019666 [patent_doc_number] => 20250157888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/510493 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510493
ELECTRONIC DEVICE Nov 14, 2023 Pending
Array ( [id] => 20276500 [patent_doc_number] => 12446289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => MOSFET device structure with air-gaps in spacer and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/507473 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 5436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/507473
MOSFET device structure with air-gaps in spacer and methods for forming the same Nov 12, 2023 Issued
Array ( [id] => 18991294 [patent_doc_number] => 20240063263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH CHANNEL AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/500225 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500225 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500225
Semiconductor device structure with channel and method for forming the same Nov 1, 2023 Issued
Array ( [id] => 18990825 [patent_doc_number] => 20240062794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => CRYSTAL SEED LAYER FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) [patent_app_type] => utility [patent_app_number] => 18/499423 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499423
Crystal seed layer for magnetic random access memory (MRAM) Oct 31, 2023 Issued
Array ( [id] => 20004629 [patent_doc_number] => 20250142851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => METHOD TO SUPPRESS BASE POLY LINKUP OVERGROWTH INTO THE EMITTER CAVITY DURING SILICON GERMANIUM SELECTIVE EPITAXY GROWTH [patent_app_type] => utility [patent_app_number] => 18/499153 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499153
METHOD TO SUPPRESS BASE POLY LINKUP OVERGROWTH INTO THE EMITTER CAVITY DURING SILICON GERMANIUM SELECTIVE EPITAXY GROWTH Oct 30, 2023 Pending
Array ( [id] => 20002426 [patent_doc_number] => 20250140648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => BONDING A WAFER WITH A SUBSTRATE TO A WAFER WITH BACKSIDE INTERCONNECT WIRING [patent_app_type] => utility [patent_app_number] => 18/495832 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495832 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/495832
BONDING A WAFER WITH A SUBSTRATE TO A WAFER WITH BACKSIDE INTERCONNECT WIRING Oct 26, 2023 Pending
Array ( [id] => 19868606 [patent_doc_number] => 20250107392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => STRETCHABLE DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 18/495960 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/495960
STRETCHABLE DISPLAY PANEL Oct 26, 2023 Pending
Array ( [id] => 19913678 [patent_doc_number] => 12289911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/378710 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 8122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378710
Semiconductor devices Oct 10, 2023 Issued
Array ( [id] => 19881300 [patent_doc_number] => 20250113557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SEMICONDUCTOR DEVICES WITH ORTHOGONAL VOLTAGE BLOCKING STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/479530 [patent_app_country] => US [patent_app_date] => 2023-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/479530
SEMICONDUCTOR DEVICES WITH ORTHOGONAL VOLTAGE BLOCKING STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES Oct 1, 2023 Pending
Array ( [id] => 19468215 [patent_doc_number] => 20240321885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/476688 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476688
INTEGRATED CIRCUIT DEVICE Sep 27, 2023 Pending
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