Search

David C. Spalla

Examiner (ID: 6816, Phone: (303)297-4298 , Office: P/2896 )

Most Active Art Unit
2896
Art Unit(s)
2818, 2821, 2815, 2896, 2893, 4148
Total Applications
1019
Issued Applications
844
Pending Applications
64
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18570742 [patent_doc_number] => 20230261079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/987126 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/987126
Semiconductor device and method of fabricating the same Nov 14, 2022 Issued
Array ( [id] => 18379758 [patent_doc_number] => 20230154847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => ADVANCED STRUCTURES HAVING MOSFET TRANSISTORS AND METAL LAYERS [patent_app_type] => utility [patent_app_number] => 18/055397 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/055397
ADVANCED STRUCTURES HAVING MOSFET TRANSISTORS AND METAL LAYERS Nov 13, 2022 Pending
Array ( [id] => 19176255 [patent_doc_number] => 20240162229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => STACKED FET WITH EXTREMELY SMALL CELL HEIGHT [patent_app_type] => utility [patent_app_number] => 18/054194 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054194 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054194
Stacked FET with extremely small cell height Nov 9, 2022 Issued
Array ( [id] => 19161302 [patent_doc_number] => 20240154009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING A BACKSIDE CONTACT WITH BACKSIDE SIDEWALL SPACERS [patent_app_type] => utility [patent_app_number] => 17/982809 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982809
SEMICONDUCTOR STRUCTURE HAVING A BACKSIDE CONTACT WITH BACKSIDE SIDEWALL SPACERS Nov 7, 2022 Pending
Array ( [id] => 18224039 [patent_doc_number] => 20230063033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Metal-Insensitive Epitaxy Formation [patent_app_type] => utility [patent_app_number] => 17/981639 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/981639
Metal-insensitive epitaxy formation Nov 6, 2022 Issued
Array ( [id] => 18196781 [patent_doc_number] => 20230050300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof [patent_app_type] => utility [patent_app_number] => 17/978576 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17978576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/978576
Optimized proximity profile for strained source/drain feature and method of fabricating thereof Oct 31, 2022 Issued
Array ( [id] => 19146548 [patent_doc_number] => 20240145578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => NANOSHEET WITH DUAL ISOLATION REGIONS SEPARATED BY BURIED INNER SPACER [patent_app_type] => utility [patent_app_number] => 18/050560 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050560
NANOSHEET WITH DUAL ISOLATION REGIONS SEPARATED BY BURIED INNER SPACER Oct 27, 2022 Pending
Array ( [id] => 19146548 [patent_doc_number] => 20240145578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => NANOSHEET WITH DUAL ISOLATION REGIONS SEPARATED BY BURIED INNER SPACER [patent_app_type] => utility [patent_app_number] => 18/050560 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050560
NANOSHEET WITH DUAL ISOLATION REGIONS SEPARATED BY BURIED INNER SPACER Oct 27, 2022 Pending
Array ( [id] => 18608264 [patent_doc_number] => 11749743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/968778 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3868 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/968778
Semiconductor device and method for fabricating the same Oct 17, 2022 Issued
Array ( [id] => 18645732 [patent_doc_number] => 11769813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/046518 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046518 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046518
Semiconductor devices Oct 13, 2022 Issued
Array ( [id] => 19101028 [patent_doc_number] => 20240120256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => Backside BPR/BSPDN Intergration with Backside Local Interconnect. [patent_app_type] => utility [patent_app_number] => 17/961281 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961281
Backside BPR/BSPDN Intergration with Backside Local Interconnect. Oct 5, 2022 Pending
Array ( [id] => 19101028 [patent_doc_number] => 20240120256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => Backside BPR/BSPDN Intergration with Backside Local Interconnect. [patent_app_type] => utility [patent_app_number] => 17/961281 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961281
Backside BPR/BSPDN Intergration with Backside Local Interconnect. Oct 5, 2022 Pending
Array ( [id] => 19101028 [patent_doc_number] => 20240120256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => Backside BPR/BSPDN Intergration with Backside Local Interconnect. [patent_app_type] => utility [patent_app_number] => 17/961281 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961281
Backside BPR/BSPDN Intergration with Backside Local Interconnect. Oct 5, 2022 Pending
Array ( [id] => 19086393 [patent_doc_number] => 20240113194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SQUARE ETCH PROFILES IN HETEROGENOUS MATERIALS OF INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 17/957580 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957580 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957580
SQUARE ETCH PROFILES IN HETEROGENOUS MATERIALS OF INTEGRATED CIRCUIT DEVICES Sep 29, 2022 Pending
Array ( [id] => 19086300 [patent_doc_number] => 20240113101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => CAPACITOR STRUCTURE EMBEDDED WITHIN SOURCE OR DRAIN REGION [patent_app_type] => utility [patent_app_number] => 17/936990 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936990
CAPACITOR STRUCTURE EMBEDDED WITHIN SOURCE OR DRAIN REGION Sep 29, 2022 Pending
Array ( [id] => 18167213 [patent_doc_number] => 20230033820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/956840 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/956840
Method for fabricating semiconductor device Sep 29, 2022 Issued
Array ( [id] => 19086393 [patent_doc_number] => 20240113194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SQUARE ETCH PROFILES IN HETEROGENOUS MATERIALS OF INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 17/957580 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957580 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957580
SQUARE ETCH PROFILES IN HETEROGENOUS MATERIALS OF INTEGRATED CIRCUIT DEVICES Sep 29, 2022 Pending
Array ( [id] => 19071128 [patent_doc_number] => 20240105554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => TRANSISTORS WITH VIA-TO-BACKSIDE POWER RAIL SPACERS [patent_app_type] => utility [patent_app_number] => 17/950361 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950361
TRANSISTORS WITH VIA-TO-BACKSIDE POWER RAIL SPACERS Sep 21, 2022 Pending
Array ( [id] => 19071128 [patent_doc_number] => 20240105554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => TRANSISTORS WITH VIA-TO-BACKSIDE POWER RAIL SPACERS [patent_app_type] => utility [patent_app_number] => 17/950361 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950361
TRANSISTORS WITH VIA-TO-BACKSIDE POWER RAIL SPACERS Sep 21, 2022 Pending
Array ( [id] => 19054912 [patent_doc_number] => 20240096881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => INTEGRATED CIRCUIT STRUCTURES HAVING GATE CUT PLUG REMOVED FROM TRENCH CONTACT USING ANGLED DIRECTIONAL ETCH [patent_app_type] => utility [patent_app_number] => 17/949861 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949861
INTEGRATED CIRCUIT STRUCTURES HAVING GATE CUT PLUG REMOVED FROM TRENCH CONTACT USING ANGLED DIRECTIONAL ETCH Sep 20, 2022 Pending
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