Search

David Corbin

Examiner (ID: 8973)

Most Active Art Unit
3501
Art Unit(s)
3501, 3504, 3506
Total Applications
1456
Issued Applications
1338
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3128483 [patent_doc_number] => 05410655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Intersystem channel paging system having a circuit for executing synchronous or asynchronous instructions for transferring messages between devices and a shared storage' [patent_app_type] => 1 [patent_app_number] => 8/305502 [patent_app_country] => US [patent_app_date] => 1994-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5386 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410655.pdf [firstpage_image] =>[orig_patent_app_number] => 305502 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/305502
Intersystem channel paging system having a circuit for executing synchronous or asynchronous instructions for transferring messages between devices and a shared storage Sep 12, 1994 Issued
Array ( [id] => 3564721 [patent_doc_number] => 05493675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Compiler back end calling predetermined front end routines that use effect and dependency indicators to provide information to the compiler to determine the validity of an optimization' [patent_app_type] => 1 [patent_app_number] => 8/249670 [patent_app_country] => US [patent_app_date] => 1994-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 36902 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493675.pdf [firstpage_image] =>[orig_patent_app_number] => 249670 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/249670
Compiler back end calling predetermined front end routines that use effect and dependency indicators to provide information to the compiler to determine the validity of an optimization May 25, 1994 Issued
Array ( [id] => 3606186 [patent_doc_number] => 05522077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Object oriented network system for allocating ranges of globally unique object identifiers from a server process to client processes which release unused identifiers' [patent_app_type] => 1 [patent_app_number] => 8/246065 [patent_app_country] => US [patent_app_date] => 1994-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7736 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/522/05522077.pdf [firstpage_image] =>[orig_patent_app_number] => 246065 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/246065
Object oriented network system for allocating ranges of globally unique object identifiers from a server process to client processes which release unused identifiers May 18, 1994 Issued
Array ( [id] => 3635944 [patent_doc_number] => 05613117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Optimizing compiler using templates corresponding to portions of an intermediate language graph to determine an order of evaluation and to allocate lifetimes to temporary names for variables' [patent_app_type] => 1 [patent_app_number] => 8/231441 [patent_app_country] => US [patent_app_date] => 1994-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 45841 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/613/05613117.pdf [firstpage_image] =>[orig_patent_app_number] => 231441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231441
Optimizing compiler using templates corresponding to portions of an intermediate language graph to determine an order of evaluation and to allocate lifetimes to temporary names for variables Apr 19, 1994 Issued
Array ( [id] => 3567074 [patent_doc_number] => 05519882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'System for configuring a disk drive as a master or slave by either cable or local selection with only one jumper block or one switching device' [patent_app_type] => 1 [patent_app_number] => 8/205971 [patent_app_country] => US [patent_app_date] => 1994-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3676 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519882.pdf [firstpage_image] =>[orig_patent_app_number] => 205971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/205971
System for configuring a disk drive as a master or slave by either cable or local selection with only one jumper block or one switching device Mar 2, 1994 Issued
Array ( [id] => 3561874 [patent_doc_number] => 05546595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Object-oriented system using objects representing hardware devices, physical connectors and connections between the physical connectors for configuring a computer' [patent_app_type] => 1 [patent_app_number] => 8/171722 [patent_app_country] => US [patent_app_date] => 1993-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11011 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546595.pdf [firstpage_image] =>[orig_patent_app_number] => 171722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/171722
Object-oriented system using objects representing hardware devices, physical connectors and connections between the physical connectors for configuring a computer Dec 20, 1993 Issued
Array ( [id] => 3117562 [patent_doc_number] => 05448699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Apparatus with leading edge delay circuit for selectively sending a delayed substitute version of a signal transmitted between an expansion card and a system bus' [patent_app_type] => 1 [patent_app_number] => 8/107206 [patent_app_country] => US [patent_app_date] => 1993-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 31683 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448699.pdf [firstpage_image] =>[orig_patent_app_number] => 107206 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/107206
Apparatus with leading edge delay circuit for selectively sending a delayed substitute version of a signal transmitted between an expansion card and a system bus Aug 15, 1993 Issued
Array ( [id] => 3672297 [patent_doc_number] => 05592623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'System for a distributed wireless star network with terminal devices and a concentrator including start bits and ORing logic for resolving transmission contention' [patent_app_type] => 1 [patent_app_number] => 8/054164 [patent_app_country] => US [patent_app_date] => 1993-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5539 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592623.pdf [firstpage_image] =>[orig_patent_app_number] => 054164 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/054164
System for a distributed wireless star network with terminal devices and a concentrator including start bits and ORing logic for resolving transmission contention Apr 25, 1993 Issued
Array ( [id] => 3533336 [patent_doc_number] => 05530903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'System for reassigning a higher priority to an interrupted user by inhibiting the access of other users until the interrupted user has completed its task' [patent_app_type] => 1 [patent_app_number] => 8/036294 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4441 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530903.pdf [firstpage_image] =>[orig_patent_app_number] => 036294 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/036294
System for reassigning a higher priority to an interrupted user by inhibiting the access of other users until the interrupted user has completed its task Mar 23, 1993 Issued
Array ( [id] => 3627313 [patent_doc_number] => 05535421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Chord keyboard system using one chord to select a group from among several groups and another chord to select a character from the selected group' [patent_app_type] => 1 [patent_app_number] => 8/033098 [patent_app_country] => US [patent_app_date] => 1993-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15171 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535421.pdf [firstpage_image] =>[orig_patent_app_number] => 033098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/033098
Chord keyboard system using one chord to select a group from among several groups and another chord to select a character from the selected group Mar 15, 1993 Issued
Array ( [id] => 3530103 [patent_doc_number] => 05577206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'System for physical layer controllers for performing automatic hardware based scrubbing of input and output dirty flags for updating system configuration changes' [patent_app_type] => 1 [patent_app_number] => 8/028342 [patent_app_country] => US [patent_app_date] => 1993-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6867 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577206.pdf [firstpage_image] =>[orig_patent_app_number] => 028342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/028342
System for physical layer controllers for performing automatic hardware based scrubbing of input and output dirty flags for updating system configuration changes Mar 8, 1993 Issued
Array ( [id] => 3564969 [patent_doc_number] => 05493689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'System for configuring an event driven interface including control blocks defining good loop locations in a memory which represent detection of a characteristic pattern' [patent_app_type] => 1 [patent_app_number] => 8/024542 [patent_app_country] => US [patent_app_date] => 1993-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 14114 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493689.pdf [firstpage_image] =>[orig_patent_app_number] => 024542 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/024542
System for configuring an event driven interface including control blocks defining good loop locations in a memory which represent detection of a characteristic pattern Feb 28, 1993 Issued
Array ( [id] => 3491232 [patent_doc_number] => 05457785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'CPU-independent and device-driver transparent system for translating a computer\'s internal bus signals onto an intermediate bus and further translating onto an expansion bus' [patent_app_type] => 1 [patent_app_number] => 8/016122 [patent_app_country] => US [patent_app_date] => 1993-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457785.pdf [firstpage_image] =>[orig_patent_app_number] => 016122 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/016122
CPU-independent and device-driver transparent system for translating a computer's internal bus signals onto an intermediate bus and further translating onto an expansion bus Feb 9, 1993 Issued
08/004568 METHOD FOR COMMUNICATION BETWEEN DATA TERMINAL EQUIPMENTS Jan 13, 1993 Abandoned
Array ( [id] => 3529650 [patent_doc_number] => 05506968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Terminating access of an agent to a shared resource when a timer, started after a low latency agent requests access, reaches a predetermined value' [patent_app_type] => 1 [patent_app_number] => 7/996992 [patent_app_country] => US [patent_app_date] => 1992-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5516 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506968.pdf [firstpage_image] =>[orig_patent_app_number] => 996992 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996992
Terminating access of an agent to a shared resource when a timer, started after a low latency agent requests access, reaches a predetermined value Dec 27, 1992 Issued
Array ( [id] => 3539580 [patent_doc_number] => 05528764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period' [patent_app_type] => 1 [patent_app_number] => 7/996277 [patent_app_country] => US [patent_app_date] => 1992-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7898 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528764.pdf [firstpage_image] =>[orig_patent_app_number] => 996277 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996277
Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period Dec 23, 1992 Issued
Array ( [id] => 3440616 [patent_doc_number] => 05463739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold' [patent_app_type] => 1 [patent_app_number] => 7/994864 [patent_app_country] => US [patent_app_date] => 1992-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463739.pdf [firstpage_image] =>[orig_patent_app_number] => 994864 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994864
Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold Dec 21, 1992 Issued
07/993372 CONFIGURABLE DISK DRIVE CONTROLLER Dec 17, 1992 Abandoned
Array ( [id] => 3530225 [patent_doc_number] => 05507004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Communication control system for either providing blank areas or overwriting areas in a receiving RAM depending on deficient or execess word counts in received frames' [patent_app_type] => 1 [patent_app_number] => 7/992774 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5493 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/507/05507004.pdf [firstpage_image] =>[orig_patent_app_number] => 992774 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/992774
Communication control system for either providing blank areas or overwriting areas in a receiving RAM depending on deficient or execess word counts in received frames Dec 17, 1992 Issued
Array ( [id] => 3585865 [patent_doc_number] => 05539913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'System for judging whether a main processor after processing an interrupt is required to process the I/O control of an I/O control local processor' [patent_app_type] => 1 [patent_app_number] => 7/973027 [patent_app_country] => US [patent_app_date] => 1992-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1975 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539913.pdf [firstpage_image] =>[orig_patent_app_number] => 973027 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/973027
System for judging whether a main processor after processing an interrupt is required to process the I/O control of an I/O control local processor Nov 5, 1992 Issued
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