David D Chung
Examiner (ID: 18063)
Most Active Art Unit | 2489 |
Art Unit(s) | 2489 |
Total Applications | 1 |
Issued Applications | 0 |
Pending Applications | 0 |
Abandoned Applications | 1 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
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[id] => 9372431
[patent_doc_number] => 20140082304
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[patent_title] => 'MONITORING A SUBSEA INSTALLATION'
[patent_app_type] => utility
[patent_app_number] => 13/990060
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[patent_app_date] => 2011-11-24
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Array
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[patent_title] => 'Memory refresh method and devices'
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Array
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[patent_title] => RAID 1--half compressed data storage
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Array
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Array
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[patent_title] => 'Level One Data Cache Line Lock and Enhanced Snoop Protocol During Cache Victims and Writebacks to Maintain Level One Data Cache and Level Two Cache Coherence'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/247209 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Sep 27, 2011 | Issued |
Array
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[patent_title] => Cloud capable storage platform with computation operating environment for storage and generic applications
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/245962 | Cloud capable storage platform with computation operating environment for storage and generic applications | Sep 26, 2011 | Issued |
Array
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[patent_title] => 'MANAGEMENT OF POINT-IN-TIME COPY RELATIONSHIP FOR EXTENT SPACE EFFICIENT VOLUMES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/245502 | Management of point-in-time copy relationship for extent space efficient volumes | Sep 25, 2011 | Issued |
Array
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[patent_title] => 'PERFORMANCE AND POWER IMPROVEMENT ON DMA WRITES TO LEVEL TWO COMBINED CACHE/SRAM THAT IS CAUSED IN LEVEL ONE DATA CACHE AND LINE IS VALID AND DIRTY'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/245183 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty | Sep 25, 2011 | Issued |
Array
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[id] => 8735109
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[patent_title] => 'SYSTEM AND METHOD FOR OPTIMIZING THERMAL MANAGEMENT FOR A STORAGE CONTROLLER CACHE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/245302 | SYSTEM AND METHOD FOR OPTIMIZING THERMAL MANAGEMENT FOR A STORAGE CONTROLLER CACHE | Sep 25, 2011 | Abandoned |
Array
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[id] => 8314885
[patent_doc_number] => 20120191916
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[patent_issue_date] => 2012-07-26
[patent_title] => 'OPTIMIZING TAG FORWARDING IN A TWO LEVEL CACHE SYSTEM FROM LEVEL ONE TO LEVER TWO CONTROLLERS FOR CACHE COHERENCE PROTOCOL FOR DIRECT MEMORY ACCESS TRANSFERS'
[patent_app_type] => utility
[patent_app_number] => 13/245206
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/245206 | Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers | Sep 25, 2011 | Issued |
Array
(
[id] => 8314892
[patent_doc_number] => 20120191915
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[patent_issue_date] => 2012-07-26
[patent_title] => 'EFFICIENT LEVEL TWO MEMORY BANKING TO IMPROVE PERFORMANCE FOR MULTIPLE SOURCE TRAFFIC AND ENABLE DEEPER PIPELINING OF ACCESSES BY REDUCING BANK STALLS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/245195 | Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls | Sep 25, 2011 | Issued |
Array
(
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Array
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Array
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Array
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Array
(
[id] => 9187015
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Array
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Array
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