Search

David D. Mattison

Examiner (ID: 5349, Phone: (303)297-4243 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2842, 2849
Total Applications
367
Issued Applications
316
Pending Applications
1
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11738732 [patent_doc_number] => 09703313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Peripheral clock management' [patent_app_type] => utility [patent_app_number] => 14/855105 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3581 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14855105 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/855105
Peripheral clock management Sep 14, 2015 Issued
Array ( [id] => 11616243 [patent_doc_number] => 09654114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Transmission circuit, integrated circuit, and parallel-to-serial conversion method' [patent_app_type] => utility [patent_app_number] => 14/854961 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4664 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854961 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854961
Transmission circuit, integrated circuit, and parallel-to-serial conversion method Sep 14, 2015 Issued
Array ( [id] => 11294451 [patent_doc_number] => 20160344383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'ADAPTIVE DUO-GATE MOSFET' [patent_app_type] => utility [patent_app_number] => 14/850982 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4721 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850982 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850982
Adaptive duo-gate MOSFET Sep 10, 2015 Issued
Array ( [id] => 11496040 [patent_doc_number] => 20170070225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'POWER GATING DEVICES AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/847387 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14902 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847387 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/847387
POWER GATING DEVICES AND METHODS Sep 7, 2015 Abandoned
Array ( [id] => 11525207 [patent_doc_number] => 09608625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Semiconductor device and semiconductor system' [patent_app_type] => utility [patent_app_number] => 14/845138 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845138 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845138
Semiconductor device and semiconductor system Sep 2, 2015 Issued
Array ( [id] => 11476571 [patent_doc_number] => 20170063355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'PACKAGE PROGRAMMABLE DECOUPLING CAPACITOR ARRAY' [patent_app_type] => utility [patent_app_number] => 14/838778 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5359 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838778 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/838778
Package programmable decoupling capacitor array Aug 27, 2015 Issued
Array ( [id] => 10803408 [patent_doc_number] => 20160149565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/839640 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4640 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14839640 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/839640
Semiconductor device and operating method thereof Aug 27, 2015 Issued
Array ( [id] => 13039705 [patent_doc_number] => 10041983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => VDS equalizer offset compensation for a current sense circuit [patent_app_type] => utility [patent_app_number] => 14/838266 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5318 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838266 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/838266
VDS equalizer offset compensation for a current sense circuit Aug 26, 2015 Issued
Array ( [id] => 12351306 [patent_doc_number] => 09952609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Low drop-out regulator circuit, chip and electronic device [patent_app_type] => utility [patent_app_number] => 15/327916 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2705 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15327916 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/327916
Low drop-out regulator circuit, chip and electronic device Aug 17, 2015 Issued
Array ( [id] => 11484292 [patent_doc_number] => 09590863 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-07 [patent_title] => 'Monitoring system control technology' [patent_app_type] => utility [patent_app_number] => 14/829298 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13153 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829298 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829298
Monitoring system control technology Aug 17, 2015 Issued
Array ( [id] => 14206401 [patent_doc_number] => 10270333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Power supply system and display apparatus [patent_app_type] => utility [patent_app_number] => 14/825191 [patent_app_country] => US [patent_app_date] => 2015-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825191 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/825191
Power supply system and display apparatus Aug 12, 2015 Issued
Array ( [id] => 14037135 [patent_doc_number] => 10230331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Digital frequency converter and method of processing in a digital frequency converter [patent_app_type] => utility [patent_app_number] => 15/329883 [patent_app_country] => US [patent_app_date] => 2015-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4568 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15329883 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/329883
Digital frequency converter and method of processing in a digital frequency converter Jul 29, 2015 Issued
Array ( [id] => 15109931 [patent_doc_number] => 10476300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Uninterruptible power supply device [patent_app_type] => utility [patent_app_number] => 15/573731 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7170 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15573731 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/573731
Uninterruptible power supply device Jul 15, 2015 Issued
Array ( [id] => 11666655 [patent_doc_number] => 20170155374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'Duplexer' [patent_app_type] => utility [patent_app_number] => 15/315368 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6550 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15315368 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/315368
Duplexer Jul 5, 2015 Issued
Array ( [id] => 10418882 [patent_doc_number] => 20150303894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'DRIVE OUTPUT HARMONIC MITIGATION DEVICES AND METHODS OF USE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/788058 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3299 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788058 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/788058
Drive output harmonic mitigation devices and methods of use thereof Jun 29, 2015 Issued
Array ( [id] => 11718868 [patent_doc_number] => 20170187367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'DEVICE AND METHOD FOR PRODUCING A DYNAMIC REFERENCE SIGNAL FOR A DRIVER CIRCUIT FOR A SEMICONDUCTOR POWER SWITCH' [patent_app_type] => utility [patent_app_number] => 15/313488 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11106 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15313488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/313488
Device and method for producing a dynamic reference signal for a driver circuit for a semiconductor power switch Jun 10, 2015 Issued
Array ( [id] => 11326598 [patent_doc_number] => 20160357210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'ON-CHIP POWER-DOMAIN SUPPLY DROOPING FOR LOW VOLTAGE IDLE/STANDBY MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/733456 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3248 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733456 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733456
On-chip power-domain supply drooping for low voltage idle/standby management Jun 7, 2015 Issued
Array ( [id] => 11733487 [patent_doc_number] => 20170194930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'QUANTUM ALGORITHMS FOR ARITHMETIC AND FUNCTION SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 15/316500 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15316500 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/316500
Quantum algorithms for arithmetic and function synthesis Jun 4, 2015 Issued
Array ( [id] => 11600470 [patent_doc_number] => 09647653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Method for reduced power clock frequency monitoring' [patent_app_type] => utility [patent_app_number] => 14/730473 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730473 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730473
Method for reduced power clock frequency monitoring Jun 3, 2015 Issued
Array ( [id] => 11412350 [patent_doc_number] => 09559669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/728741 [patent_app_country] => US [patent_app_date] => 2015-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14728741 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/728741
Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit Jun 1, 2015 Issued
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