Search

David E. Choi

Examiner (ID: 17677, Phone: (571)270-3780 , Office: P/2174 )

Most Active Art Unit
2174
Art Unit(s)
2148, 2174, 2173
Total Applications
796
Issued Applications
600
Pending Applications
61
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7278781 [patent_doc_number] => 20040061158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Semiconductor device having different thickness gate oxides' [patent_app_type] => new [patent_app_number] => 10/369625 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2780 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061158.pdf [firstpage_image] =>[orig_patent_app_number] => 10369625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369625
Semiconductor device having different thickness gate oxides Feb 20, 2003 Issued
Array ( [id] => 1119734 [patent_doc_number] => 06797580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method for fabricating a bipolar transistor in a BiCMOS process and related structure' [patent_app_type] => B1 [patent_app_number] => 10/371706 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3850 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797580.pdf [firstpage_image] =>[orig_patent_app_number] => 10371706 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/371706
Method for fabricating a bipolar transistor in a BiCMOS process and related structure Feb 20, 2003 Issued
Array ( [id] => 7448010 [patent_doc_number] => 20040164346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Power switching transistor with low drain to gate capacitance' [patent_app_type] => new [patent_app_number] => 10/369236 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164346.pdf [firstpage_image] =>[orig_patent_app_number] => 10369236 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/369236
Power switching transistor with low drain to gate capacitance Feb 19, 2003 Abandoned
Array ( [id] => 931381 [patent_doc_number] => 06979885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Devices with patterned wells and method for forming same' [patent_app_type] => utility [patent_app_number] => 10/360374 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4205 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979885.pdf [firstpage_image] =>[orig_patent_app_number] => 10360374 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360374
Devices with patterned wells and method for forming same Feb 5, 2003 Issued
Array ( [id] => 7260086 [patent_doc_number] => 20040150029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Double-gate FinFET device and fabricating method thereof' [patent_app_type] => new [patent_app_number] => 10/358981 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6825 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150029.pdf [firstpage_image] =>[orig_patent_app_number] => 10358981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358981
Double-gate FinFET device and fabricating method thereof Feb 3, 2003 Issued
Array ( [id] => 7260192 [patent_doc_number] => 20040150056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Gate metal recess for oxidation protection and parasitic capacitance reduction' [patent_app_type] => new [patent_app_number] => 10/355726 [patent_app_country] => US [patent_app_date] => 2003-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2119 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150056.pdf [firstpage_image] =>[orig_patent_app_number] => 10355726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/355726
Gate metal recess for oxidation protection and parasitic capacitance reduction Jan 30, 2003 Issued
Array ( [id] => 7260376 [patent_doc_number] => 20040150094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Stacked structure of integrated circuits' [patent_app_type] => new [patent_app_number] => 10/356185 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1435 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150094.pdf [firstpage_image] =>[orig_patent_app_number] => 10356185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356185
Stacked structure of integrated circuits Jan 29, 2003 Abandoned
Array ( [id] => 7380139 [patent_doc_number] => 20040036122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/346976 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3885 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20040036122.pdf [firstpage_image] =>[orig_patent_app_number] => 10346976 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/346976
Semiconductor device having high electron mobility comprising a SiGe/Si/SiGe substrate Jan 20, 2003 Issued
Array ( [id] => 996856 [patent_doc_number] => 06914298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Double diffusion MOSFET with N+ and P+ type regions at an equal potential' [patent_app_type] => utility [patent_app_number] => 10/346806 [patent_app_country] => US [patent_app_date] => 2003-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3705 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914298.pdf [firstpage_image] =>[orig_patent_app_number] => 10346806 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/346806
Double diffusion MOSFET with N+ and P+ type regions at an equal potential Jan 16, 2003 Issued
Array ( [id] => 1083408 [patent_doc_number] => 06833586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'LDMOS transistor with high voltage source and drain terminals' [patent_app_type] => B2 [patent_app_number] => 10/336567 [patent_app_country] => US [patent_app_date] => 2003-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3895 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833586.pdf [firstpage_image] =>[orig_patent_app_number] => 10336567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336567
LDMOS transistor with high voltage source and drain terminals Jan 1, 2003 Issued
Array ( [id] => 6849328 [patent_doc_number] => 20030141530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/329643 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10400 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20030141530.pdf [firstpage_image] =>[orig_patent_app_number] => 10329643 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329643
High breakdown voltage CMOS device Dec 25, 2002 Issued
Array ( [id] => 6841129 [patent_doc_number] => 20030146476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/329851 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10189 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20030146476.pdf [firstpage_image] =>[orig_patent_app_number] => 10329851 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329851
Large current capacity semiconductor device Dec 25, 2002 Issued
Array ( [id] => 6854147 [patent_doc_number] => 20030127648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Semiconductor device and method for producing it' [patent_app_type] => new [patent_app_number] => 10/323772 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7863 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20030127648.pdf [firstpage_image] =>[orig_patent_app_number] => 10323772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/323772
Semiconductor device Dec 19, 2002 Issued
Array ( [id] => 7125205 [patent_doc_number] => 20050056949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Discrete semiconductor component' [patent_app_type] => utility [patent_app_number] => 10/500765 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1081 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20050056949.pdf [firstpage_image] =>[orig_patent_app_number] => 10500765 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/500765
Discrete semiconductor component Dec 17, 2002 Abandoned
Array ( [id] => 1040922 [patent_doc_number] => 06870221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Power switching transistor with low drain to gate capacitance' [patent_app_type] => utility [patent_app_number] => 10/313225 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2165 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870221.pdf [firstpage_image] =>[orig_patent_app_number] => 10313225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313225
Power switching transistor with low drain to gate capacitance Dec 8, 2002 Issued
Array ( [id] => 7286422 [patent_doc_number] => 20040108545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Ion implantation methods and transistor cell layout for fin type transistors' [patent_app_type] => new [patent_app_number] => 10/065955 [patent_app_country] => US [patent_app_date] => 2002-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 3044 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20040108545.pdf [firstpage_image] =>[orig_patent_app_number] => 10065955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065955
Ion implantation methods and transistor cell layout for fin type transistors Dec 3, 2002 Issued
Array ( [id] => 1203499 [patent_doc_number] => 06720633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'High withstand voltage insulated gate N-channel field effect transistor' [patent_app_type] => B2 [patent_app_number] => 10/306696 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6192 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720633.pdf [firstpage_image] =>[orig_patent_app_number] => 10306696 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/306696
High withstand voltage insulated gate N-channel field effect transistor Nov 26, 2002 Issued
Array ( [id] => 1159485 [patent_doc_number] => 06762457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'LDMOS device having a tapered oxide' [patent_app_type] => B2 [patent_app_number] => 10/300254 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1523 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762457.pdf [firstpage_image] =>[orig_patent_app_number] => 10300254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300254
LDMOS device having a tapered oxide Nov 19, 2002 Issued
Array ( [id] => 7459347 [patent_doc_number] => 20040094804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Method and process to make multiple-threshold metal gates CMOS technology' [patent_app_type] => new [patent_app_number] => 10/300165 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6045 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094804.pdf [firstpage_image] =>[orig_patent_app_number] => 10300165 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300165
Method and process to make multiple-threshold metal gates CMOS technology Nov 19, 2002 Issued
Array ( [id] => 6760468 [patent_doc_number] => 20030123829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Monolithic integrated circuit including a waveguide and quantum well inversion channel devices and a method of fabricating same' [patent_app_type] => new [patent_app_number] => 10/292127 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6585 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20030123829.pdf [firstpage_image] =>[orig_patent_app_number] => 10292127 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292127
Monolithic integrated circuit including a waveguide and quantum well inversion channel devices and a method of fabricating same Nov 11, 2002 Issued
Menu