Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16509441 [patent_doc_number] => 20200388697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => REPLACEMENT GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 17/000615 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/000615
Replacement gate structures for advanced integrated circuit structure fabrication Aug 23, 2020 Issued
Array ( [id] => 17048164 [patent_doc_number] => 11101354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Method for forming semiconductor device structure with metal silicide layer [patent_app_type] => utility [patent_app_number] => 16/983369 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 46 [patent_no_of_words] => 5719 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983369
Method for forming semiconductor device structure with metal silicide layer Aug 2, 2020 Issued
Array ( [id] => 16479776 [patent_doc_number] => 10854732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Dual metal gate structures for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 16/908468 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908468
Dual metal gate structures for advanced integrated circuit structure fabrication Jun 21, 2020 Issued
Array ( [id] => 16280322 [patent_doc_number] => 10763364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-01 [patent_title] => Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods [patent_app_type] => utility [patent_app_number] => 16/895909 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 12803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895909 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895909
Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods Jun 7, 2020 Issued
Array ( [id] => 16609204 [patent_doc_number] => 10910217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Method for manufacturing semiconductor device, non-transitory computer-readable recording medium, and substrate processing apparatus [patent_app_type] => utility [patent_app_number] => 16/887527 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9582 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 719 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887527
Method for manufacturing semiconductor device, non-transitory computer-readable recording medium, and substrate processing apparatus May 28, 2020 Issued
Array ( [id] => 16348084 [patent_doc_number] => 20200312735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => COOLING OF ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 16/829210 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829210
COOLING OF ELECTRONIC DEVICES Mar 24, 2020 Abandoned
Array ( [id] => 16308610 [patent_doc_number] => 10777417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Dressing device, polishing apparatus, holder, housing and dressing method [patent_app_type] => utility [patent_app_number] => 16/822411 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9901 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/822411
Dressing device, polishing apparatus, holder, housing and dressing method Mar 17, 2020 Issued
Array ( [id] => 16746451 [patent_doc_number] => 10971452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Semiconductor package including electromagnetic interference shielding layer [patent_app_type] => utility [patent_app_number] => 16/773490 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773490 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/773490
Semiconductor package including electromagnetic interference shielding layer Jan 26, 2020 Issued
Array ( [id] => 17224927 [patent_doc_number] => 11177437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Alignment through topography on intermediate component for memory device patterning [patent_app_type] => utility [patent_app_number] => 16/684672 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5646 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684672
Alignment through topography on intermediate component for memory device patterning Nov 14, 2019 Issued
Array ( [id] => 17224927 [patent_doc_number] => 11177437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Alignment through topography on intermediate component for memory device patterning [patent_app_type] => utility [patent_app_number] => 16/684672 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5646 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684672
Alignment through topography on intermediate component for memory device patterning Nov 14, 2019 Issued
Array ( [id] => 17224927 [patent_doc_number] => 11177437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Alignment through topography on intermediate component for memory device patterning [patent_app_type] => utility [patent_app_number] => 16/684672 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5646 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684672
Alignment through topography on intermediate component for memory device patterning Nov 14, 2019 Issued
Array ( [id] => 15532515 [patent_doc_number] => 20200058563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => SHARED CONTACT TRENCH COMPRISING DUAL SILICIDE LAYERS AND DUAL EPITAXIAL LAYERS FOR SOURCE/DRAIN LAYERS OF NFET AND PFET DEVICES [patent_app_type] => utility [patent_app_number] => 16/599723 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599723 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599723
Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices Oct 10, 2019 Issued
Array ( [id] => 15217949 [patent_doc_number] => 20190371661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/541040 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541040 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541040
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Aug 13, 2019 Abandoned
Array ( [id] => 14691889 [patent_doc_number] => 20190245060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 16/386202 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16386202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/386202
Gate cut and fin trim isolation for advanced integrated circuit structure fabrication Apr 15, 2019 Issued
Array ( [id] => 14627495 [patent_doc_number] => 20190227115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/368778 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368778 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368778
Semiconductor device Mar 27, 2019 Issued
Array ( [id] => 14587707 [patent_doc_number] => 20190221462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Substrate Breakage Detection in a Thermal Processing System [patent_app_type] => utility [patent_app_number] => 16/362154 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362154 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362154
Substrate breakage detection in a thermal processing system Mar 21, 2019 Issued
Array ( [id] => 16316139 [patent_doc_number] => 20200294877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => Molded Semiconductor Package with Mold Surface Modification [patent_app_type] => utility [patent_app_number] => 16/355245 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355245 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355245
Molded Semiconductor Package with Mold Surface Modification Mar 14, 2019 Abandoned
Array ( [id] => 16316518 [patent_doc_number] => 20200295256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => REPLACEMENT BOTTOM ELECTRODE STRUCTURE PROCESS TO FORM MISALIGNMENT TOLERATE MRAM WITH HIGH YIELD [patent_app_type] => utility [patent_app_number] => 16/355148 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355148
Replacement bottom electrode structure process to form misalignment tolerate MRAM with high yield Mar 14, 2019 Issued
Array ( [id] => 16479764 [patent_doc_number] => 10854720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Semiconductor device manufacturing method [patent_app_type] => utility [patent_app_number] => 16/262352 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5363 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262352
Semiconductor device manufacturing method Jan 29, 2019 Issued
Array ( [id] => 15315269 [patent_doc_number] => 10522348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Methods for device fabrication using pitch reduction [patent_app_type] => utility [patent_app_number] => 16/249369 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 10403 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249369
Methods for device fabrication using pitch reduction Jan 15, 2019 Issued
Menu