
David E. Graybill
Examiner (ID: 353, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2812, 2814, 1107, 2822, 3727, 2827, 1763, 2894 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12354951
[patent_doc_number] => 09953829
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-24
[patent_title] => Image processing apparatus with improved slide printout based on layout data
[patent_app_type] => utility
[patent_app_number] => 15/002483
[patent_app_country] => US
[patent_app_date] => 2016-01-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/002483 | Image processing apparatus with improved slide printout based on layout data | Jan 20, 2016 | Issued |
Array
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[patent_kind] => A1
[patent_issue_date] => 2017-07-27
[patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 15/002405
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[patent_app_date] => 2016-01-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/002405 | Method for fabricating semiconductor package | Jan 20, 2016 | Issued |
Array
(
[id] => 11904464
[patent_doc_number] => 09773906
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[patent_issue_date] => 2017-09-26
[patent_title] => 'Relaxed semiconductor layers with reduced defects and methods of forming the same'
[patent_app_type] => utility
[patent_app_number] => 15/002078
[patent_app_country] => US
[patent_app_date] => 2016-01-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/002078 | Relaxed semiconductor layers with reduced defects and methods of forming the same | Jan 19, 2016 | Issued |
Array
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[patent_issue_date] => 2016-11-15
[patent_title] => 'Method of forming split-gate memory cell array along with low and high voltage logic devices'
[patent_app_type] => utility
[patent_app_number] => 15/002307
[patent_app_country] => US
[patent_app_date] => 2016-01-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/002307 | Method of forming split-gate memory cell array along with low and high voltage logic devices | Jan 19, 2016 | Issued |
Array
(
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[patent_issue_date] => 2016-10-20
[patent_title] => 'METHOD OF FORMING A TEST STRUCTURE FOR DETECTING BAD PATTERNS, AND METHOD OF DETECTING BAD PATTERNS USING THE SAME'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/000644 | METHOD OF FORMING A TEST STRUCTURE FOR DETECTING BAD PATTERNS, AND METHOD OF DETECTING BAD PATTERNS USING THE SAME | Jan 18, 2016 | Abandoned |
Array
(
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[patent_issue_date] => 2016-05-12
[patent_title] => 'MASK SET HAVING FEATURE PATTERNS AND DUMMY PATTERNS'
[patent_app_type] => utility
[patent_app_number] => 14/996232
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Array
(
[id] => 11746586
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[patent_title] => 'POROUS UNDERFILL ENABLING REWORK'
[patent_app_type] => utility
[patent_app_number] => 14/990902
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[patent_app_date] => 2016-01-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/990902 | POROUS UNDERFILL ENABLING REWORK | Jan 7, 2016 | Abandoned |
Array
(
[id] => 13950889
[patent_doc_number] => 10211223
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-19
[patent_title] => Vertical ferroelectric memory device and a method for manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 14/998227
[patent_app_country] => US
[patent_app_date] => 2015-12-23
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/998227 | Vertical ferroelectric memory device and a method for manufacturing thereof | Dec 22, 2015 | Issued |
Array
(
[id] => 10984489
[patent_doc_number] => 20160181435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'FLOATING GATE TRANSISTORS AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/968353
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/968353 | FLOATING GATE TRANSISTORS AND METHOD FOR FORMING THE SAME | Dec 13, 2015 | Abandoned |
Array
(
[id] => 12936367
[patent_doc_number] => 09831354
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-28
[patent_title] => Split-gate flash memory having mirror structure and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 14/968108
[patent_app_country] => US
[patent_app_date] => 2015-12-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/968108 | Split-gate flash memory having mirror structure and method for forming the same | Dec 13, 2015 | Issued |
Array
(
[id] => 11681361
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[patent_issue_date] => 2017-06-13
[patent_title] => 'Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same'
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[patent_app_number] => 14/968297
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/968297 | Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same | Dec 13, 2015 | Issued |
Array
(
[id] => 10826144
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[patent_issue_date] => 2016-06-16
[patent_title] => 'SUBSTRATE WITH A SUPPORTING PLATE AND FABRICATION METHOD THEREOF'
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Array
(
[id] => 11660137
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[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-06
[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/968169 | Semiconductor device and manufacturing method thereof | Dec 13, 2015 | Issued |
| 14/968133 | CONTACTING SOI SUBSTRATES | Dec 13, 2015 | Abandoned |
Array
(
[id] => 11694370
[patent_doc_number] => 20170170087
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[patent_title] => 'ELECTRONIC PACKAGE THAT INCLUDES MULTIPLE SUPPORTS'
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[patent_app_number] => 14/967993
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/967993 | ELECTRONIC PACKAGE THAT INCLUDES MULTIPLE SUPPORTS | Dec 13, 2015 | Abandoned |
Array
(
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[patent_title] => 'Solder bumps formed on wafers using preformed solder balls with different compositions and sizes'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/967610 | Solder bumps formed on wafers using preformed solder balls with different compositions and sizes | Dec 13, 2015 | Issued |
Array
(
[id] => 11817853
[patent_doc_number] => 09721812
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[patent_title] => 'Optical device with precoated underfill'
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Array
(
[id] => 12051373
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Array
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Array
(
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