Search

David E. Graybill

Examiner (ID: 353, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2812, 2814, 1107, 2822, 3727, 2827, 1763, 2894
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12354951 [patent_doc_number] => 09953829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Image processing apparatus with improved slide printout based on layout data [patent_app_type] => utility [patent_app_number] => 15/002483 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6153 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002483 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002483
Image processing apparatus with improved slide printout based on layout data Jan 20, 2016 Issued
Array ( [id] => 11824803 [patent_doc_number] => 20170213740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/002405 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4030 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002405 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002405
Method for fabricating semiconductor package Jan 20, 2016 Issued
Array ( [id] => 11904464 [patent_doc_number] => 09773906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Relaxed semiconductor layers with reduced defects and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 15/002078 [patent_app_country] => US [patent_app_date] => 2016-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002078
Relaxed semiconductor layers with reduced defects and methods of forming the same Jan 19, 2016 Issued
Array ( [id] => 11279885 [patent_doc_number] => 09496369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Method of forming split-gate memory cell array along with low and high voltage logic devices' [patent_app_type] => utility [patent_app_number] => 15/002307 [patent_app_country] => US [patent_app_date] => 2016-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3158 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002307
Method of forming split-gate memory cell array along with low and high voltage logic devices Jan 19, 2016 Issued
Array ( [id] => 11110841 [patent_doc_number] => 20160307811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'METHOD OF FORMING A TEST STRUCTURE FOR DETECTING BAD PATTERNS, AND METHOD OF DETECTING BAD PATTERNS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/000644 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 9168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15000644 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/000644
METHOD OF FORMING A TEST STRUCTURE FOR DETECTING BAD PATTERNS, AND METHOD OF DETECTING BAD PATTERNS USING THE SAME Jan 18, 2016 Abandoned
Array ( [id] => 10785812 [patent_doc_number] => 20160131969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'MASK SET HAVING FEATURE PATTERNS AND DUMMY PATTERNS' [patent_app_type] => utility [patent_app_number] => 14/996232 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3852 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14996232 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/996232
MASK SET HAVING FEATURE PATTERNS AND DUMMY PATTERNS Jan 14, 2016 Abandoned
Array ( [id] => 11746586 [patent_doc_number] => 20170200659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'POROUS UNDERFILL ENABLING REWORK' [patent_app_type] => utility [patent_app_number] => 14/990902 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4815 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990902 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990902
POROUS UNDERFILL ENABLING REWORK Jan 7, 2016 Abandoned
Array ( [id] => 13950889 [patent_doc_number] => 10211223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Vertical ferroelectric memory device and a method for manufacturing thereof [patent_app_type] => utility [patent_app_number] => 14/998227 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8003 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998227 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998227
Vertical ferroelectric memory device and a method for manufacturing thereof Dec 22, 2015 Issued
Array ( [id] => 10984489 [patent_doc_number] => 20160181435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'FLOATING GATE TRANSISTORS AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/968353 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968353 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968353
FLOATING GATE TRANSISTORS AND METHOD FOR FORMING THE SAME Dec 13, 2015 Abandoned
Array ( [id] => 12936367 [patent_doc_number] => 09831354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Split-gate flash memory having mirror structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 14/968108 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4817 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968108 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968108
Split-gate flash memory having mirror structure and method for forming the same Dec 13, 2015 Issued
Array ( [id] => 11681361 [patent_doc_number] => 09679896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/968297 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 65 [patent_no_of_words] => 14964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968297 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968297
Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same Dec 13, 2015 Issued
Array ( [id] => 10826144 [patent_doc_number] => 20160172313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SUBSTRATE WITH A SUPPORTING PLATE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/967986 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967986 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967986
SUBSTRATE WITH A SUPPORTING PLATE AND FABRICATION METHOD THEREOF Dec 13, 2015 Abandoned
Array ( [id] => 11660137 [patent_doc_number] => 09673149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/968169 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4419 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968169 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968169
Semiconductor device and manufacturing method thereof Dec 13, 2015 Issued
14/968133 CONTACTING SOI SUBSTRATES Dec 13, 2015 Abandoned
Array ( [id] => 11694370 [patent_doc_number] => 20170170087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'ELECTRONIC PACKAGE THAT INCLUDES MULTIPLE SUPPORTS' [patent_app_type] => utility [patent_app_number] => 14/967993 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967993 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967993
ELECTRONIC PACKAGE THAT INCLUDES MULTIPLE SUPPORTS Dec 13, 2015 Abandoned
Array ( [id] => 11817961 [patent_doc_number] => 09721919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Solder bumps formed on wafers using preformed solder balls with different compositions and sizes' [patent_app_type] => utility [patent_app_number] => 14/967610 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 7610 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 480 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967610 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967610
Solder bumps formed on wafers using preformed solder balls with different compositions and sizes Dec 13, 2015 Issued
Array ( [id] => 11817853 [patent_doc_number] => 09721812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Optical device with precoated underfill' [patent_app_type] => utility [patent_app_number] => 14/947855 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3730 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947855 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/947855
Optical device with precoated underfill Nov 19, 2015 Issued
Array ( [id] => 12051373 [patent_doc_number] => 20170327717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'ADHESIVE COMPOUNDS CONTAINING GETTER MATERIALS THAT CAN BE ACTIVATED' [patent_app_type] => utility [patent_app_number] => 15/520003 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 12208 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/520003
ADHESIVE COMPOUNDS CONTAINING GETTER MATERIALS THAT CAN BE ACTIVATED Oct 14, 2015 Abandoned
Array ( [id] => 10689522 [patent_doc_number] => 20160035668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'AUTOMATED SHORT LENGHT WIRE SHAPE STRAPPING AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/882484 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5080 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882484 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882484
AUTOMATED SHORT LENGHT WIRE SHAPE STRAPPING AND METHODS OF FABRICATING THE SAME Oct 13, 2015 Abandoned
Array ( [id] => 11539400 [patent_doc_number] => 09613816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/875409 [patent_app_country] => US [patent_app_date] => 2015-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/875409
Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device Oct 4, 2015 Issued
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