
David E. Graybill
Examiner (ID: 6012)
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2812, 1107, 2822, 2827, 1763, 3727, 2894, 2814 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9654266
[patent_doc_number] => 20140225271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'PANELIZED PACKAGING WITH TRANSFERRED DIELECTRIC'
[patent_app_type] => utility
[patent_app_number] => 14/261265
[patent_app_country] => US
[patent_app_date] => 2014-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4255
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261265
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/261265 | PANELIZED PACKAGING WITH TRANSFERRED DIELECTRIC | Apr 23, 2014 | Abandoned |
Array
(
[id] => 9654276
[patent_doc_number] => 20140225282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'SYSTEM IN PACKAGE (SIP) WITH DUAL LAMINATE INTERPOSERS'
[patent_app_type] => utility
[patent_app_number] => 14/258875
[patent_app_country] => US
[patent_app_date] => 2014-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258875
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/258875 | System in package (SIP) with dual laminate interposers | Apr 21, 2014 | Issued |
Array
(
[id] => 9909656
[patent_doc_number] => 20150064857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-05
[patent_title] => 'MASK FOR EXPOSURE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING DISPLAY PANEL USING THE MASK'
[patent_app_type] => utility
[patent_app_number] => 14/224284
[patent_app_country] => US
[patent_app_date] => 2014-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/224284 | MASK FOR EXPOSURE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING DISPLAY PANEL USING THE MASK | Mar 24, 2014 | Abandoned |
Array
(
[id] => 9839072
[patent_doc_number] => 20150031153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-29
[patent_title] => 'SPUTTERING TARGET, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING AN ORGANIC LIGHT EMITTING DISPLAY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/223605
[patent_app_country] => US
[patent_app_date] => 2014-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/223605 | Sputtering target, method of fabricating the same, and method of fabricating an organic light emitting display apparatus | Mar 23, 2014 | Issued |
Array
(
[id] => 9460309
[patent_doc_number] => 20140124734
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/154149
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[patent_app_date] => 2014-01-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/154149 | Nitride-based semiconductor light-emitting device | Jan 12, 2014 | Issued |
Array
(
[id] => 10107024
[patent_doc_number] => 09142807
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-22
[patent_title] => 'Method for manufacturing flexible OLED (organic light emitting display) panel'
[patent_app_type] => utility
[patent_app_number] => 14/241071
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[patent_app_date] => 2014-01-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/241071 | Method for manufacturing flexible OLED (organic light emitting display) panel | Jan 12, 2014 | Issued |
Array
(
[id] => 11638060
[patent_doc_number] => 09660046
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[patent_issue_date] => 2017-05-23
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/438824
[patent_app_country] => US
[patent_app_date] => 2014-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/438824 | Method of manufacturing semiconductor device | Jan 8, 2014 | Issued |
Array
(
[id] => 11551577
[patent_doc_number] => 09620433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-11
[patent_title] => 'Packaged microelectronic elements having blind vias for heat dissipation'
[patent_app_type] => utility
[patent_app_number] => 14/145288
[patent_app_country] => US
[patent_app_date] => 2013-12-31
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/145288 | Packaged microelectronic elements having blind vias for heat dissipation | Dec 30, 2013 | Issued |
Array
(
[id] => 9418862
[patent_doc_number] => 20140103512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-17
[patent_title] => 'Dual-leadframe Multi-chip Package'
[patent_app_type] => utility
[patent_app_number] => 14/106654
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/106654 | Dual-leadframe multi-chip package | Dec 12, 2013 | Issued |
Array
(
[id] => 9491212
[patent_doc_number] => 20140141618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-22
[patent_title] => 'PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY'
[patent_app_type] => utility
[patent_app_number] => 14/097956
[patent_app_country] => US
[patent_app_date] => 2013-12-05
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14097956
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/097956 | Processing for overcoming extreme topography | Dec 4, 2013 | Issued |
Array
(
[id] => 11346529
[patent_doc_number] => 09530945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-27
[patent_title] => 'Integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 14/089539
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/089539 | Integrated circuit device | Nov 24, 2013 | Issued |
Array
(
[id] => 9368018
[patent_doc_number] => 20140077891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-20
[patent_title] => 'CRYSTAL OSCILLATOR EMULATOR WITH EXTERNALLY SELECTABLE OPERATING CONFIGURATIONS'
[patent_app_type] => utility
[patent_app_number] => 14/089261
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089261
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/089261 | Crystal oscillator emulator with externally selectable operating configurations | Nov 24, 2013 | Issued |
Array
(
[id] => 10255801
[patent_doc_number] => 20150140798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'SEMICONDUCTOR MANUFACTURING METHOD AND EQUIPMENT THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/080880 | SEMICONDUCTOR MANUFACTURING METHOD AND EQUIPMENT THEREOF | Nov 14, 2013 | Abandoned |
Array
(
[id] => 10255799
[patent_doc_number] => 20150140796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'FORMATION OF CONTACT/VIA HOLE WITH SELF-ALIGNMENT'
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[patent_app_number] => 14/081894
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/081894 | Formation of contact/via hole with self-alignment | Nov 14, 2013 | Issued |
Array
(
[id] => 10145063
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[patent_issue_date] => 2015-11-03
[patent_title] => 'Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/081623 | Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device | Nov 14, 2013 | Issued |
Array
(
[id] => 10247866
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[patent_issue_date] => 2015-05-14
[patent_title] => 'IN-SITU RELAXATION FOR IMPROVED CMOS PRODUCT LIFETIME'
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[patent_app_number] => 14/077723
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/077723 | In-situ relaxation for improved CMOS product lifetime | Nov 11, 2013 | Issued |
Array
(
[id] => 10358437
[patent_doc_number] => 20150243443
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[patent_title] => 'PHOTOSEMICONDUCTOR ELECTRODE, PHOTOELECTROCHEMICAL CELL, AND ENERGY SYSTEM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/431585 | PHOTOSEMICONDUCTOR ELECTRODE, PHOTOELECTROCHEMICAL CELL, AND ENERGY SYSTEM | Oct 27, 2013 | Abandoned |
Array
(
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[patent_title] => 'PROCESS FOR GROWING AT LEAST ONE NANOWIRE USING A TRANSITION METAL NITRIDE LAYER OBTAINED IN TWO STEPS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/438480 | Process for growing at least one nanowire using a transition metal nitride layer obtained in two steps | Oct 24, 2013 | Issued |
Array
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[patent_title] => 'METHOD FOR FABRICATING AN INTER DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/059756 | Method for fabricating an inter dielectric layer in semiconductor device | Oct 21, 2013 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/054834 | METHOD FOR FORMING DAMASCENE OPENING AND APPLICATIONS THEREOF | Oct 15, 2013 | Abandoned |