David E. Graybill

Array ( [id] => 8496272 [patent_doc_number] => 20120295680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'MULTI-LAYERED ELECTRONIC PUZZLE' [patent_app_type] => utility [patent_app_number] => 13/535575 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2454 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8513722 [patent_doc_number] => 20120313130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'SOLID STATE LIGHT EMITTER WITH PUMPED NANOPHOSPHORS FOR PRODUCING HIGH CRI WHITE LIGHT' [patent_app_type] => utility [patent_app_number] => 13/526231 [patent_app_country] => US [patent_app_date] => 2012-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8822 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13526231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9839107 [patent_doc_number] => 20150031188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'METHOD FOR ISOLATING ACTIVE REGIONS IN GERMANIUM-BASED MOS DEVICE' [patent_app_type] => utility [patent_app_number] => 14/344050 [patent_app_country] => US [patent_app_date] => 2012-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2516 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14344050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8725402 [patent_doc_number] => 08404517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/485729 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 14557 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13485729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8393743 [patent_doc_number] => 20120231582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'DEVICE INCLUDING A SEMICONDUCTOR CHIP' [patent_app_type] => utility [patent_app_number] => 13/477740 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10437 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8492449 [patent_doc_number] => 20120291856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'BARRIER FILMS AND HIGH THROUGHPUT MANUFACTURING PROCESSES FOR PHOTOVOLTAIC DEVICES' [patent_app_type] => utility [patent_app_number] => 13/442771 [patent_app_country] => US [patent_app_date] => 2012-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 20272 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8796946 [patent_doc_number] => 08435813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Light emitting device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/438323 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4412 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8299133 [patent_doc_number] => 20120181689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices' [patent_app_type] => utility [patent_app_number] => 13/430577 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6884 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8287461 [patent_doc_number] => 20120175784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound' [patent_app_type] => utility [patent_app_number] => 13/424484 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12159 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8261876 [patent_doc_number] => 20120161304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Dual-leadframe Multi-chip Package and Method of Manufacture' [patent_app_type] => utility [patent_app_number] => 13/411990 [patent_app_country] => US [patent_app_date] => 2012-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5994 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13411990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16324228 [patent_doc_number] => 10784200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Ionizing radiation blocking in IC chip to reduce soft errors [patent_app_type] => utility [patent_app_number] => 13/409643 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2923 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13409643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8249126 [patent_doc_number] => 20120153452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'Double-Sided Semiconductor Device and Method of Forming Top-Side and Bottom-Side Interconnect Structures' [patent_app_type] => utility [patent_app_number] => 13/408715 [patent_app_country] => US [patent_app_date] => 2012-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6528 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153452.pdf [firstpage_image] =>[orig_patent_app_number] => 13408715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10831246 [patent_doc_number] => 08859414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Electronic assemblies including mechanically secured protruding bonding conductor joints' [patent_app_type] => utility [patent_app_number] => 13/397844 [patent_app_country] => US [patent_app_date] => 2012-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6077 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9964723 [patent_doc_number] => 09012334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Formation of a tantalum-nitride layer' [patent_app_type] => utility [patent_app_number] => 13/396311 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13396311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8237070 [patent_doc_number] => 20120145799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/372877 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 19801 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13372877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8166276 [patent_doc_number] => 20120104511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS' [patent_app_type] => utility [patent_app_number] => 13/349203 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5778 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104511.pdf [firstpage_image] =>[orig_patent_app_number] => 13349203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8166348 [patent_doc_number] => 20120104550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'HIGH ASPECT RATIO CONTACTS' [patent_app_type] => utility [patent_app_number] => 13/347192 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104550.pdf [firstpage_image] =>[orig_patent_app_number] => 13347192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8166514 [patent_doc_number] => 20120104634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'CHIP PACKAGE STRUCTURE AND MANUFACTURING METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/346567 [patent_app_country] => US [patent_app_date] => 2012-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104634.pdf [firstpage_image] =>[orig_patent_app_number] => 13346567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9648444 [patent_doc_number] => 08802454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Methods of manufacturing a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 13/331702 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8139793 [patent_doc_number] => 20120094441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'Semiconductor Chip Attach Configuration Having Improved Thermal Characteristics' [patent_app_type] => utility [patent_app_number] => 13/330195 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4286 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20120094441.pdf [firstpage_image] =>[orig_patent_app_number] => 13330195 [rel_patent_id] =>[rel_patent_doc_number] =>)