
David E. Graybill
Examiner (ID: 12341, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 3727, 2812, 1107, 2827, 2814, 1763, 2822 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4771972
[patent_doc_number] => 20080057630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Flexible core for enhancement of package interconnect reliablity'
[patent_app_type] => utility
[patent_app_number] => 11/978059
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20080057630.pdf
[firstpage_image] =>[orig_patent_app_number] => 11978059
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/978059 | Flexible core for enhancement of package interconnect reliablity | Oct 25, 2007 | Abandoned |
Array
(
[id] => 4648773
[patent_doc_number] => 20080036028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS'
[patent_app_type] => utility
[patent_app_number] => 11/877048
[patent_app_country] => US
[patent_app_date] => 2007-10-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0036/20080036028.pdf
[firstpage_image] =>[orig_patent_app_number] => 11877048
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/877048 | DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS | Oct 22, 2007 | Abandoned |
Array
(
[id] => 5439367
[patent_doc_number] => 20090091006
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-09
[patent_title] => 'Dual Capillary IC Wirebonding'
[patent_app_type] => utility
[patent_app_number] => 11/867228
[patent_app_country] => US
[patent_app_date] => 2007-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4738
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[pdf_file] => publications/A1/0091/20090091006.pdf
[firstpage_image] =>[orig_patent_app_number] => 11867228
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/867228 | Dual capillary IC wirebonding | Oct 3, 2007 | Issued |
Array
(
[id] => 5425885
[patent_doc_number] => 20090085195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'Method of Making Microelectronic Package Using Integrated Heat Spreader Stiffener Panel and Microelectronic Package Formed According to the Method'
[patent_app_type] => utility
[patent_app_number] => 11/864279
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2922
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[pdf_file] => publications/A1/0085/20090085195.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864279
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864279 | Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method | Sep 27, 2007 | Issued |
Array
(
[id] => 5425859
[patent_doc_number] => 20090085169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS'
[patent_app_type] => utility
[patent_app_number] => 11/864899
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0085/20090085169.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864899
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864899 | METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS | Sep 27, 2007 | Abandoned |
Array
(
[id] => 7540333
[patent_doc_number] => 08058176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-15
[patent_title] => 'Methods of patterning insulating layers using etching techniques that compensate for etch rate variations'
[patent_app_type] => utility
[patent_app_number] => 11/861478
[patent_app_country] => US
[patent_app_date] => 2007-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4585
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[pdf_file] => patents/08/058/08058176.pdf
[firstpage_image] =>[orig_patent_app_number] => 11861478
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861478 | Methods of patterning insulating layers using etching techniques that compensate for etch rate variations | Sep 25, 2007 | Issued |
Array
(
[id] => 5505775
[patent_doc_number] => 20090078982
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'ALPHA HYDROXY CARBOXYLIC ACID ETCHANTS FOR SILICON MICROSTRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 11/860519
[patent_app_country] => US
[patent_app_date] => 2007-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0078/20090078982.pdf
[firstpage_image] =>[orig_patent_app_number] => 11860519
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/860519 | ALPHA HYDROXY CARBOXYLIC ACID ETCHANTS FOR SILICON MICROSTRUCTURES | Sep 23, 2007 | Abandoned |
Array
(
[id] => 5505875
[patent_doc_number] => 20090079082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'BONDING PAD STRUCTURE ALLOWING WIRE BONDING OVER AN ACTIVE AREA IN A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/860217
[patent_app_country] => US
[patent_app_date] => 2007-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2261
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[pdf_file] => publications/A1/0079/20090079082.pdf
[firstpage_image] =>[orig_patent_app_number] => 11860217
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/860217 | BONDING PAD STRUCTURE ALLOWING WIRE BONDING OVER AN ACTIVE AREA IN A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME | Sep 23, 2007 | Abandoned |
Array
(
[id] => 4462450
[patent_doc_number] => 07880301
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/902217
[patent_app_country] => US
[patent_app_date] => 2007-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/880/07880301.pdf
[firstpage_image] =>[orig_patent_app_number] => 11902217
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/902217 | Semiconductor device and method for manufacturing the same | Sep 19, 2007 | Issued |
Array
(
[id] => 5508652
[patent_doc_number] => 20090081859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'Metallization process'
[patent_app_type] => utility
[patent_app_number] => 11/902228
[patent_app_country] => US
[patent_app_date] => 2007-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0081/20090081859.pdf
[firstpage_image] =>[orig_patent_app_number] => 11902228
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/902228 | Metallization process | Sep 19, 2007 | Abandoned |
Array
(
[id] => 4571631
[patent_doc_number] => 07829461
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/898409
[patent_app_country] => US
[patent_app_date] => 2007-09-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/829/07829461.pdf
[firstpage_image] =>[orig_patent_app_number] => 11898409
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/898409 | Method for fabricating semiconductor device | Sep 11, 2007 | Issued |
Array
(
[id] => 4772063
[patent_doc_number] => 20080057721
[patent_country] => US
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[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11847679
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/847679 | Method of fabricating semiconductor device | Aug 29, 2007 | Issued |
Array
(
[id] => 4772041
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[patent_title] => 'Method for manufacturing semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/893909 | Method for manufacturing semiconductor device | Aug 16, 2007 | Abandoned |
Array
(
[id] => 121521
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Array
(
[id] => 6519423
[patent_doc_number] => 20100230821
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[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/377610 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD | Aug 12, 2007 | Abandoned |
Array
(
[id] => 5413628
[patent_doc_number] => 20090039515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-12
[patent_title] => 'IONIZING RADIATION BLOCKING IN IC CHIP TO REDUCE SOFT ERRORS'
[patent_app_type] => utility
[patent_app_number] => 11/836819
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[patent_app_date] => 2007-08-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/836819 | Ionizing radiation blocking in IC chip to reduce soft errors | Aug 9, 2007 | Issued |
Array
(
[id] => 4907184
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[patent_title] => 'METHODS OF FORMING RUTHENIUM FILM BY CHANGING PROCESS CONDITIONS DURING CHEMICAL VAPOR DEPOSITION AND RUTHENIUM FILMS FORMED THEREBY'
[patent_app_type] => utility
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Array
(
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[patent_title] => 'LARGE AREA FLAT IMAGE SENSOR ASSEMBLY'
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Array
(
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[patent_title] => 'LEAD FRAME'
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[firstpage_image] =>[orig_patent_app_number] => 11833247
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/833247 | LEAD FRAME | Aug 2, 2007 | Abandoned |
Array
(
[id] => 4533735
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[patent_kind] => B2
[patent_issue_date] => 2011-02-15
[patent_title] => 'Fabrication of substrates with a useful layer of monocrystalline semiconductor material'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/831484 | Fabrication of substrates with a useful layer of monocrystalline semiconductor material | Jul 30, 2007 | Issued |