Search

David E. Graybill

Examiner (ID: 12341, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 3727, 2812, 1107, 2827, 2814, 1763, 2822
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4771972 [patent_doc_number] => 20080057630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Flexible core for enhancement of package interconnect reliablity' [patent_app_type] => utility [patent_app_number] => 11/978059 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4489 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057630.pdf [firstpage_image] =>[orig_patent_app_number] => 11978059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/978059
Flexible core for enhancement of package interconnect reliablity Oct 25, 2007 Abandoned
Array ( [id] => 4648773 [patent_doc_number] => 20080036028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS' [patent_app_type] => utility [patent_app_number] => 11/877048 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5671 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036028.pdf [firstpage_image] =>[orig_patent_app_number] => 11877048 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877048
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS Oct 22, 2007 Abandoned
Array ( [id] => 5439367 [patent_doc_number] => 20090091006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Dual Capillary IC Wirebonding' [patent_app_type] => utility [patent_app_number] => 11/867228 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4738 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091006.pdf [firstpage_image] =>[orig_patent_app_number] => 11867228 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867228
Dual capillary IC wirebonding Oct 3, 2007 Issued
Array ( [id] => 5425885 [patent_doc_number] => 20090085195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Method of Making Microelectronic Package Using Integrated Heat Spreader Stiffener Panel and Microelectronic Package Formed According to the Method' [patent_app_type] => utility [patent_app_number] => 11/864279 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2922 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085195.pdf [firstpage_image] =>[orig_patent_app_number] => 11864279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864279
Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method Sep 27, 2007 Issued
Array ( [id] => 5425859 [patent_doc_number] => 20090085169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS' [patent_app_type] => utility [patent_app_number] => 11/864899 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3126 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085169.pdf [firstpage_image] =>[orig_patent_app_number] => 11864899 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864899
METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS Sep 27, 2007 Abandoned
Array ( [id] => 7540333 [patent_doc_number] => 08058176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Methods of patterning insulating layers using etching techniques that compensate for etch rate variations' [patent_app_type] => utility [patent_app_number] => 11/861478 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4585 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/058/08058176.pdf [firstpage_image] =>[orig_patent_app_number] => 11861478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861478
Methods of patterning insulating layers using etching techniques that compensate for etch rate variations Sep 25, 2007 Issued
Array ( [id] => 5505775 [patent_doc_number] => 20090078982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'ALPHA HYDROXY CARBOXYLIC ACID ETCHANTS FOR SILICON MICROSTRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/860519 [patent_app_country] => US [patent_app_date] => 2007-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2883 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20090078982.pdf [firstpage_image] =>[orig_patent_app_number] => 11860519 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860519
ALPHA HYDROXY CARBOXYLIC ACID ETCHANTS FOR SILICON MICROSTRUCTURES Sep 23, 2007 Abandoned
Array ( [id] => 5505875 [patent_doc_number] => 20090079082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'BONDING PAD STRUCTURE ALLOWING WIRE BONDING OVER AN ACTIVE AREA IN A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 11/860217 [patent_app_country] => US [patent_app_date] => 2007-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2261 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20090079082.pdf [firstpage_image] =>[orig_patent_app_number] => 11860217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860217
BONDING PAD STRUCTURE ALLOWING WIRE BONDING OVER AN ACTIVE AREA IN A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME Sep 23, 2007 Abandoned
Array ( [id] => 4462450 [patent_doc_number] => 07880301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/902217 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5601 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/880/07880301.pdf [firstpage_image] =>[orig_patent_app_number] => 11902217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902217
Semiconductor device and method for manufacturing the same Sep 19, 2007 Issued
Array ( [id] => 5508652 [patent_doc_number] => 20090081859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Metallization process' [patent_app_type] => utility [patent_app_number] => 11/902228 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2111 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20090081859.pdf [firstpage_image] =>[orig_patent_app_number] => 11902228 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902228
Metallization process Sep 19, 2007 Abandoned
Array ( [id] => 4571631 [patent_doc_number] => 07829461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/898409 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 5751 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/829/07829461.pdf [firstpage_image] =>[orig_patent_app_number] => 11898409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/898409
Method for fabricating semiconductor device Sep 11, 2007 Issued
Array ( [id] => 4772063 [patent_doc_number] => 20080057721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/847679 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057721.pdf [firstpage_image] =>[orig_patent_app_number] => 11847679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847679
Method of fabricating semiconductor device Aug 29, 2007 Issued
Array ( [id] => 4772041 [patent_doc_number] => 20080057699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/893909 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057699.pdf [firstpage_image] =>[orig_patent_app_number] => 11893909 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/893909
Method for manufacturing semiconductor device Aug 16, 2007 Abandoned
Array ( [id] => 121521 [patent_doc_number] => 07709353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Method for producing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/893458 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 5245 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/709/07709353.pdf [firstpage_image] =>[orig_patent_app_number] => 11893458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/893458
Method for producing semiconductor device Aug 15, 2007 Issued
Array ( [id] => 6519423 [patent_doc_number] => 20100230821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD' [patent_app_type] => utility [patent_app_number] => 12/377610 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3136 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230821.pdf [firstpage_image] =>[orig_patent_app_number] => 12377610 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/377610
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD Aug 12, 2007 Abandoned
Array ( [id] => 5413628 [patent_doc_number] => 20090039515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'IONIZING RADIATION BLOCKING IN IC CHIP TO REDUCE SOFT ERRORS' [patent_app_type] => utility [patent_app_number] => 11/836819 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2776 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20090039515.pdf [firstpage_image] =>[orig_patent_app_number] => 11836819 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/836819
Ionizing radiation blocking in IC chip to reduce soft errors Aug 9, 2007 Issued
Array ( [id] => 4907184 [patent_doc_number] => 20080017950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'METHODS OF FORMING RUTHENIUM FILM BY CHANGING PROCESS CONDITIONS DURING CHEMICAL VAPOR DEPOSITION AND RUTHENIUM FILMS FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 11/835481 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6873 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20080017950.pdf [firstpage_image] =>[orig_patent_app_number] => 11835481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/835481
METHODS OF FORMING RUTHENIUM FILM BY CHANGING PROCESS CONDITIONS DURING CHEMICAL VAPOR DEPOSITION AND RUTHENIUM FILMS FORMED THEREBY Aug 7, 2007 Abandoned
Array ( [id] => 4800495 [patent_doc_number] => 20080012082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'LARGE AREA FLAT IMAGE SENSOR ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 11/835480 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3924 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20080012082.pdf [firstpage_image] =>[orig_patent_app_number] => 11835480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/835480
LARGE AREA FLAT IMAGE SENSOR ASSEMBLY Aug 7, 2007 Abandoned
Array ( [id] => 4749236 [patent_doc_number] => 20080157307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'LEAD FRAME' [patent_app_type] => utility [patent_app_number] => 11/833247 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7090 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157307.pdf [firstpage_image] =>[orig_patent_app_number] => 11833247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833247
LEAD FRAME Aug 2, 2007 Abandoned
Array ( [id] => 4533735 [patent_doc_number] => 07888235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Fabrication of substrates with a useful layer of monocrystalline semiconductor material' [patent_app_type] => utility [patent_app_number] => 11/831484 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5235 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888235.pdf [firstpage_image] =>[orig_patent_app_number] => 11831484 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831484
Fabrication of substrates with a useful layer of monocrystalline semiconductor material Jul 30, 2007 Issued
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