David E. Graybill

Array ( [id] => 4629244 [patent_doc_number] => 08008130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board' [patent_app_type] => utility [patent_app_number] => 11/727025 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 158 [patent_figures_cnt] => 158 [patent_no_of_words] => 67950 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/008/08008130.pdf [firstpage_image] =>[orig_patent_app_number] => 11727025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 270460 [patent_doc_number] => 07563696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Semiconductor device manufacturing apparatus and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/690089 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6973 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563696.pdf [firstpage_image] =>[orig_patent_app_number] => 11690089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5275566 [patent_doc_number] => 20090127698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'COMPOSITE CONTACT FOR FINE PITCH ELECTRICAL INTERCONNECT ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 12/293499 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7220 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127698.pdf [firstpage_image] =>[orig_patent_app_number] => 12293499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5256805 [patent_doc_number] => 20070210437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/714906 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7293 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210437.pdf [firstpage_image] =>[orig_patent_app_number] => 11714906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4691203 [patent_doc_number] => 20080083973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Lead frame for an optical semiconductor device, optical semiconductor device using the same, and manufacturing method for these' [patent_app_type] => utility [patent_app_number] => 11/714916 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6628 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083973.pdf [firstpage_image] =>[orig_patent_app_number] => 11714916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4695575 [patent_doc_number] => 20080217759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Chip package substrate and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/715146 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217759.pdf [firstpage_image] =>[orig_patent_app_number] => 11715146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4663724 [patent_doc_number] => 20080254631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/680709 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9450 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254631.pdf [firstpage_image] =>[orig_patent_app_number] => 11680709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11239899 [patent_doc_number] => 09466545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-11 [patent_title] => 'Semiconductor package in package' [patent_app_type] => utility [patent_app_number] => 11/677506 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5698 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11677506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5250652 [patent_doc_number] => 20070132108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'METHOD FOR MANUFACTURING A WAFER LEVEL CHIP SCALE PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/677478 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4101 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132108.pdf [firstpage_image] =>[orig_patent_app_number] => 11677478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8398750 [patent_doc_number] => 08269132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Method for electrical discharge machining of electrically non-conductive material' [patent_app_type] => utility [patent_app_number] => 12/225518 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3894 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12225518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4870759 [patent_doc_number] => 20080197493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Integrated circuit including conductive bumps' [patent_app_type] => utility [patent_app_number] => 11/707427 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4412 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197493.pdf [firstpage_image] =>[orig_patent_app_number] => 11707427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5186126 [patent_doc_number] => 20070164433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Ball grid array package' [patent_app_type] => utility [patent_app_number] => 11/705265 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3949 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164433.pdf [firstpage_image] =>[orig_patent_app_number] => 11705265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 122640 [patent_doc_number] => 07709853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Packaged semiconductor light emitting devices having multiple optical elements' [patent_app_type] => utility [patent_app_number] => 11/705305 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8328 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/709/07709853.pdf [firstpage_image] =>[orig_patent_app_number] => 11705305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5095673 [patent_doc_number] => 20070117282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Thin film transistor and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/651668 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12030 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117282.pdf [firstpage_image] =>[orig_patent_app_number] => 11651668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10002169 [patent_doc_number] => 09046252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'LED lamp' [patent_app_type] => utility [patent_app_number] => 12/160836 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2993 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12160836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4971461 [patent_doc_number] => 20070111463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER' [patent_app_type] => utility [patent_app_number] => 11/620663 [patent_app_country] => US [patent_app_date] => 2007-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3941 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111463.pdf [firstpage_image] =>[orig_patent_app_number] => 11620663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4483654 [patent_doc_number] => 07902014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'CMOS devices with a single work function gate electrode and method of fabrication' [patent_app_type] => utility [patent_app_number] => 11/649545 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6988 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902014.pdf [firstpage_image] =>[orig_patent_app_number] => 11649545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5077019 [patent_doc_number] => 20070120243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Assembly jig and manufacturing method of multilayer semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/646158 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5572 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120243.pdf [firstpage_image] =>[orig_patent_app_number] => 11646158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 122650 [patent_doc_number] => 07704812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Semiconductor circuit and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/607021 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 61 [patent_no_of_words] => 16936 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704812.pdf [firstpage_image] =>[orig_patent_app_number] => 11607021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4971384 [patent_doc_number] => 20070111386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices' [patent_app_type] => utility [patent_app_number] => 11/603521 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111386.pdf [firstpage_image] =>[orig_patent_app_number] => 11603521 [rel_patent_id] =>[rel_patent_doc_number] =>)