Search

David E. Graybill

Examiner (ID: 12341, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 3727, 2812, 1107, 2827, 2814, 1763, 2822
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4451105 [patent_doc_number] => 07964428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Micromechanical component and method for fabricating a micromechanical component' [patent_app_type] => utility [patent_app_number] => 11/887470 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5750 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964428.pdf [firstpage_image] =>[orig_patent_app_number] => 11887470 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/887470
Micromechanical component and method for fabricating a micromechanical component Apr 2, 2006 Issued
Array ( [id] => 5834790 [patent_doc_number] => 20060246621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Microelectronic die including thermally conductive structure in a substrate thereof and method of forming same' [patent_app_type] => utility [patent_app_number] => 11/395109 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3578 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20060246621.pdf [firstpage_image] =>[orig_patent_app_number] => 11395109 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/395109
Microelectronic die including thermally conductive structure in a substrate thereof and method of forming same Mar 30, 2006 Abandoned
Array ( [id] => 4974767 [patent_doc_number] => 20070215997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Chip-scale package' [patent_app_type] => utility [patent_app_number] => 11/378607 [patent_app_country] => US [patent_app_date] => 2006-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2276 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20070215997.pdf [firstpage_image] =>[orig_patent_app_number] => 11378607 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378607
Chip-scale package Mar 16, 2006 Abandoned
Array ( [id] => 5631666 [patent_doc_number] => 20060148136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Patterned plasma treatment to improve distribution of underfill material' [patent_app_type] => utility [patent_app_number] => 11/374496 [patent_app_country] => US [patent_app_date] => 2006-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5072 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148136.pdf [firstpage_image] =>[orig_patent_app_number] => 11374496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/374496
Patterned plasma treatment to improve distribution of underfill material Mar 12, 2006 Issued
Array ( [id] => 5256792 [patent_doc_number] => 20070210424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/276647 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210424.pdf [firstpage_image] =>[orig_patent_app_number] => 11276647 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/276647
Integrated circuit package in package system Mar 7, 2006 Issued
Array ( [id] => 5683032 [patent_doc_number] => 20060199302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Semiconductor device and a manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 11/367297 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 20802 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199302.pdf [firstpage_image] =>[orig_patent_app_number] => 11367297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367297
Semiconductor device and a manufacturing method of the same Mar 5, 2006 Abandoned
Array ( [id] => 5677943 [patent_doc_number] => 20060183299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Electronic device sealed under vacuum containing a getter and method of operation' [patent_app_type] => utility [patent_app_number] => 11/367529 [patent_app_country] => US [patent_app_date] => 2006-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4733 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20060183299.pdf [firstpage_image] =>[orig_patent_app_number] => 11367529 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367529
Electronic device sealed under vacuum containing a getter and method of operation Mar 1, 2006 Abandoned
Array ( [id] => 586144 [patent_doc_number] => 07463831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Transponder assembly for use with parallel optics modules in fiber optic communications systems' [patent_app_type] => utility [patent_app_number] => 11/350432 [patent_app_country] => US [patent_app_date] => 2006-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4500 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463831.pdf [firstpage_image] =>[orig_patent_app_number] => 11350432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/350432
Transponder assembly for use with parallel optics modules in fiber optic communications systems Feb 8, 2006 Issued
Array ( [id] => 5160026 [patent_doc_number] => 20070173070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'POROUS LOW-K DIELECTRIC FILM AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/307167 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3105 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20070173070.pdf [firstpage_image] =>[orig_patent_app_number] => 11307167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/307167
POROUS LOW-K DIELECTRIC FILM AND FABRICATION METHOD THEREOF Jan 25, 2006 Abandoned
Array ( [id] => 8675323 [patent_doc_number] => 08383436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Manufacturing method for semiconductor chips, and semiconductor chip' [patent_app_type] => utility [patent_app_number] => 11/792669 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 48 [patent_no_of_words] => 15639 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11792669 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/792669
Manufacturing method for semiconductor chips, and semiconductor chip Jan 22, 2006 Issued
Array ( [id] => 5652914 [patent_doc_number] => 20060138649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package' [patent_app_type] => utility [patent_app_number] => 11/337168 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 28486 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138649.pdf [firstpage_image] =>[orig_patent_app_number] => 11337168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/337168
Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package Jan 19, 2006 Abandoned
Array ( [id] => 340556 [patent_doc_number] => 07500431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'System, method, and apparatus for membrane, pad, and stamper architecture for uniform base layer and nanoimprinting pressure' [patent_app_type] => utility [patent_app_number] => 11/331367 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2597 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/500/07500431.pdf [firstpage_image] =>[orig_patent_app_number] => 11331367 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/331367
System, method, and apparatus for membrane, pad, and stamper architecture for uniform base layer and nanoimprinting pressure Jan 11, 2006 Issued
Array ( [id] => 281719 [patent_doc_number] => 07553719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Flash memory device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/320677 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2662 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553719.pdf [firstpage_image] =>[orig_patent_app_number] => 11320677 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/320677
Flash memory device and method for fabricating the same Dec 29, 2005 Issued
Array ( [id] => 5631715 [patent_doc_number] => 20060148185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method for manufacturing high voltage transistor' [patent_app_type] => utility [patent_app_number] => 11/320727 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3055 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148185.pdf [firstpage_image] =>[orig_patent_app_number] => 11320727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/320727
Method for manufacturing high voltage transistor Dec 29, 2005 Abandoned
Array ( [id] => 5035547 [patent_doc_number] => 20070100086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method of fabricating a three-dimensional nanostructure' [patent_app_type] => utility [patent_app_number] => 11/322877 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3619 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20070100086.pdf [firstpage_image] =>[orig_patent_app_number] => 11322877 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322877
Method of fabricating a three-dimensional nanostructure Dec 28, 2005 Abandoned
Array ( [id] => 5631767 [patent_doc_number] => 20060148237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/320337 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1825 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148237.pdf [firstpage_image] =>[orig_patent_app_number] => 11320337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/320337
Method for fabricating a semiconductor device Dec 28, 2005 Abandoned
Array ( [id] => 5022891 [patent_doc_number] => 20070148857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Independently controlled, double gate nanowire memory cell with self-aligned contacts' [patent_app_type] => utility [patent_app_number] => 11/321147 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3760 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148857.pdf [firstpage_image] =>[orig_patent_app_number] => 11321147 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321147
Independently controlled, double gate nanowire memory cell with self-aligned contacts Dec 27, 2005 Issued
Array ( [id] => 5022924 [patent_doc_number] => 20070148890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Oxygen enhanced metastable silicon germanium film layer' [patent_app_type] => utility [patent_app_number] => 11/318797 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3893 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148890.pdf [firstpage_image] =>[orig_patent_app_number] => 11318797 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/318797
Oxygen enhanced metastable silicon germanium film layer Dec 26, 2005 Abandoned
Array ( [id] => 9020370 [patent_doc_number] => 08530355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Mixed orientation semiconductor device and method' [patent_app_type] => utility [patent_app_number] => 11/317737 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3465 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11317737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317737
Mixed orientation semiconductor device and method Dec 22, 2005 Issued
Array ( [id] => 5655924 [patent_doc_number] => 20060141660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'CMOS image sensor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/315147 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2446 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141660.pdf [firstpage_image] =>[orig_patent_app_number] => 11315147 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/315147
CMOS image sensor and method for fabricating the same Dec 22, 2005 Abandoned
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