
David E. Graybill
Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_title] => 'Structure and method for III-nitride device isolation'
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11437055
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Array
(
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[patent_title] => 'Method and apparatus for cleaning and sealing display packages'
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Array
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[patent_issue_date] => 2008-12-16
[patent_title] => 'Memory packages having stair step interconnection layers'
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[patent_app_date] => 2006-05-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/381357 | Memory packages having stair step interconnection layers | May 1, 2006 | Issued |
Array
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[patent_title] => 'Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectonic devices'
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Array
(
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[patent_title] => 'Method Of Fabricating Isolated Semiconductor Devices In Epi-Less Substrate'
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Array
(
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[patent_title] => 'Micromechanical component and method for fabricating a micromechanical component'
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Array
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[patent_title] => 'Microelectronic die including thermally conductive structure in a substrate thereof and method of forming same'
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[patent_app_number] => 11/395109
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[patent_app_date] => 2006-03-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/395109 | Microelectronic die including thermally conductive structure in a substrate thereof and method of forming same | Mar 30, 2006 | Abandoned |
Array
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[id] => 4974767
[patent_doc_number] => 20070215997
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[patent_issue_date] => 2007-09-20
[patent_title] => 'Chip-scale package'
[patent_app_type] => utility
[patent_app_number] => 11/378607
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[patent_app_date] => 2006-03-17
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Array
(
[id] => 5631666
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[patent_issue_date] => 2006-07-06
[patent_title] => 'Patterned plasma treatment to improve distribution of underfill material'
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[patent_app_number] => 11/374496
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/374496 | Patterned plasma treatment to improve distribution of underfill material | Mar 12, 2006 | Issued |
Array
(
[id] => 5256792
[patent_doc_number] => 20070210424
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[patent_issue_date] => 2007-09-13
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/276647
[patent_app_country] => US
[patent_app_date] => 2006-03-08
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[firstpage_image] =>[orig_patent_app_number] => 11276647
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/276647 | Integrated circuit package in package system | Mar 7, 2006 | Issued |
Array
(
[id] => 5683032
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[patent_title] => 'Semiconductor device and a manufacturing method of the same'
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Array
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Array
(
[id] => 586144
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[patent_title] => 'Transponder assembly for use with parallel optics modules in fiber optic communications systems'
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Array
(
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[patent_title] => 'POROUS LOW-K DIELECTRIC FILM AND FABRICATION METHOD THEREOF'
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Array
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Array
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[id] => 5652914
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[patent_title] => 'Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/337168 | Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package | Jan 19, 2006 | Abandoned |
Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/320337 | Method for fabricating a semiconductor device | Dec 28, 2005 | Abandoned |