David E. Graybill

Array ( [id] => 14024559 [patent_doc_number] => 20190074273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/033252 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15370059 [patent_doc_number] => 20200020794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/033256 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13909035 [patent_doc_number] => 20190043722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SUBSTRATE TREATMENT METHOD, COMPUTER STORAGE MEDIUM AND SUBSTRATE TREATMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/033537 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13543189 [patent_doc_number] => 20180323141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => LOW-DISPERSION COMPONENT IN AN ELECTRONIC CHIP [patent_app_type] => utility [patent_app_number] => 16/033109 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13951885 [patent_doc_number] => 10211727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-19 [patent_title] => Circuit for level shifting a clock signal using a voltage multiplier [patent_app_type] => utility [patent_app_number] => 16/028814 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 6816 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15922677 [patent_doc_number] => 10658589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Alignment through topography on intermediate component for memory device patterning [patent_app_type] => utility [patent_app_number] => 16/019798 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5616 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13493893 [patent_doc_number] => 20180298489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => DEPOSITION APPARATUS, METHOD FOR CONTROLLING SAME, DEPOSITION METHOD USING DEPOSITION APPARATUS, AND DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 16/015946 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13451689 [patent_doc_number] => 20180277387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => GASES FOR LOW DAMAGE SELECTIVE SILICON NITRIDE ETCHING [patent_app_type] => utility [patent_app_number] => 15/995758 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15995758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15123421 [patent_doc_number] => 20190348344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/974547 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15123749 [patent_doc_number] => 20190348508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHODS FOR CHAMFERING WORK FUNCTION MATERIAL LAYERS IN GATE CAVITIES HAVING VARYING WIDTHS [patent_app_type] => utility [patent_app_number] => 15/974037 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16803308 [patent_doc_number] => 10998261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Over-molded IC package with in-mold capacitor [patent_app_type] => utility [patent_app_number] => 15/974493 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 7274 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13378777 [patent_doc_number] => 20180240930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => METHOD AND APPARATUS FOR MANUFACTURING LEAD WIRE FOR SOLAR CELL [patent_app_type] => utility [patent_app_number] => 15/959486 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16607464 [patent_doc_number] => 10908465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Array substrate and display device [patent_app_type] => utility [patent_app_number] => 16/097538 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2619 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16097538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16147995 [patent_doc_number] => 10707074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Method for manufacturing semiconductor device, non-transitory computer-readable recording medium, and substrate processing apparatus [patent_app_type] => utility [patent_app_number] => 15/933104 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9566 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13451717 [patent_doc_number] => 20180277401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 15/933237 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14843123 [patent_doc_number] => 20190279962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => METHOD AND APPARATUS FOR STACKING WARPED CHIPS TO ASSEMBLE THREE-DIMENSIONAL INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/917195 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15917195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13963207 [patent_doc_number] => 20190057948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/911183 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12896044 [patent_doc_number] => 20180190523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => Substrate Breakage Detection in a Thermal Processing System [patent_app_type] => utility [patent_app_number] => 15/909231 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13335167 [patent_doc_number] => 20180219121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => Method for the Cryogenic Processing of Solar Cells and Solar Panel Components [patent_app_type] => utility [patent_app_number] => 15/881915 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12716839 [patent_doc_number] => 20180130779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => METHOD OF FORMING AN ARRAY OF A MULTI-DEVICE UNIT CELL [patent_app_type] => utility [patent_app_number] => 15/861896 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15861896 [rel_patent_id] =>[rel_patent_doc_number] =>)