Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7086571 [patent_doc_number] => 20050006683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Capacitor and method for fabricating ferroelectric memory device with the same' [patent_app_type] => utility [patent_app_number] => 10/899171 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4161 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20050006683.pdf [firstpage_image] =>[orig_patent_app_number] => 10899171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899171
Capacitor and method for fabricating ferroelectric memory device with the same Jul 26, 2004 Abandoned
Array ( [id] => 7430436 [patent_doc_number] => 20040266223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Laser irradiation method, laser irradiation apparatus, and method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/896007 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14743 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266223.pdf [firstpage_image] =>[orig_patent_app_number] => 10896007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/896007
Laser irradiation method, laser irradiation apparatus, and method of manufacturing a semiconductor device Jul 21, 2004 Issued
10/890377 System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process Jul 12, 2004 Abandoned
Array ( [id] => 637776 [patent_doc_number] => 07125740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Solid-state image pickup device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 10/889157 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 47 [patent_no_of_words] => 9203 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/125/07125740.pdf [firstpage_image] =>[orig_patent_app_number] => 10889157 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889157
Solid-state image pickup device and fabrication method thereof Jul 11, 2004 Issued
Array ( [id] => 5738647 [patent_doc_number] => 20060009038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Processing for overcoming extreme topography' [patent_app_type] => utility [patent_app_number] => 10/889437 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20060009038.pdf [firstpage_image] =>[orig_patent_app_number] => 10889437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889437
Processing for overcoming extreme topography Jul 11, 2004 Abandoned
Array ( [id] => 8027187 [patent_doc_number] => 08142673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Compositions for dissolution of low-k dielectric films, and methods of use' [patent_app_type] => utility [patent_app_number] => 10/889597 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5486 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/142/08142673.pdf [firstpage_image] =>[orig_patent_app_number] => 10889597 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889597
Compositions for dissolution of low-k dielectric films, and methods of use Jul 11, 2004 Issued
Array ( [id] => 7022575 [patent_doc_number] => 20050016969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Laser-irradiated metallized electroceramic' [patent_app_type] => utility [patent_app_number] => 10/885877 [patent_app_country] => US [patent_app_date] => 2004-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6292 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20050016969.pdf [firstpage_image] =>[orig_patent_app_number] => 10885877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/885877
Laser-irradiated metallized electroceramic Jul 7, 2004 Issued
Array ( [id] => 534110 [patent_doc_number] => 07172930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer' [patent_app_type] => utility [patent_app_number] => 10/883887 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3922 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/172/07172930.pdf [firstpage_image] =>[orig_patent_app_number] => 10883887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/883887
Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer Jul 1, 2004 Issued
Array ( [id] => 7061213 [patent_doc_number] => 20050003574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Method of creating a high performance organic semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/884317 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7995 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20050003574.pdf [firstpage_image] =>[orig_patent_app_number] => 10884317 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884317
Method of creating a high performance organic semiconductor device Jun 30, 2004 Abandoned
Array ( [id] => 432256 [patent_doc_number] => 07265029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Fabrication of substrates with a useful layer of monocrystalline semiconductor material' [patent_app_type] => utility [patent_app_number] => 10/883437 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4835 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265029.pdf [firstpage_image] =>[orig_patent_app_number] => 10883437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/883437
Fabrication of substrates with a useful layer of monocrystalline semiconductor material Jun 30, 2004 Issued
Array ( [id] => 1022563 [patent_doc_number] => 06888229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Connection components with frangible leads and bus' [patent_app_type] => utility [patent_app_number] => 10/872105 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 15116 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888229.pdf [firstpage_image] =>[orig_patent_app_number] => 10872105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/872105
Connection components with frangible leads and bus Jun 17, 2004 Issued
Array ( [id] => 766202 [patent_doc_number] => 07008820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Chip scale package with open substrate' [patent_app_type] => utility [patent_app_number] => 10/866561 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3300 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/008/07008820.pdf [firstpage_image] =>[orig_patent_app_number] => 10866561 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866561
Chip scale package with open substrate Jun 9, 2004 Issued
Array ( [id] => 7349209 [patent_doc_number] => 20040248401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Method for forming buried wiring and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/859217 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8431 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20040248401.pdf [firstpage_image] =>[orig_patent_app_number] => 10859217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859217
Method for forming buried wiring and semiconductor device Jun 2, 2004 Abandoned
Array ( [id] => 7375860 [patent_doc_number] => 20040219763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices' [patent_app_type] => new [patent_app_number] => 10/855032 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6403 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20040219763.pdf [firstpage_image] =>[orig_patent_app_number] => 10855032 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/855032
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices May 25, 2004 Issued
Array ( [id] => 7429317 [patent_doc_number] => 20040209453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof' [patent_app_type] => new [patent_app_number] => 10/847614 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3655 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209453.pdf [firstpage_image] =>[orig_patent_app_number] => 10847614 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847614
Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof May 17, 2004 Abandoned
Array ( [id] => 721194 [patent_doc_number] => 07044461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method and apparatus for adjustably induced biaxial strain' [patent_app_type] => utility [patent_app_number] => 10/837027 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8515 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/044/07044461.pdf [firstpage_image] =>[orig_patent_app_number] => 10837027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/837027
Method and apparatus for adjustably induced biaxial strain Apr 29, 2004 Issued
Array ( [id] => 7184311 [patent_doc_number] => 20040203244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Electronic component and fabricating method' [patent_app_type] => new [patent_app_number] => 10/834707 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4850 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20040203244.pdf [firstpage_image] =>[orig_patent_app_number] => 10834707 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834707
Electronic component and fabricating method Apr 28, 2004 Abandoned
Array ( [id] => 7729357 [patent_doc_number] => 08101459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween' [patent_app_type] => utility [patent_app_number] => 10/834651 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 18 [patent_no_of_words] => 6015 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/101/08101459.pdf [firstpage_image] =>[orig_patent_app_number] => 10834651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834651
Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween Apr 28, 2004 Issued
Array ( [id] => 6952299 [patent_doc_number] => 20050227394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Method for forming die protecting layer' [patent_app_type] => utility [patent_app_number] => 10/818156 [patent_app_country] => US [patent_app_date] => 2004-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1473 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20050227394.pdf [firstpage_image] =>[orig_patent_app_number] => 10818156 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/818156
Method for forming die protecting layer Apr 2, 2004 Abandoned
Array ( [id] => 7442566 [patent_doc_number] => 20040185612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Semiconductor device and process of production of same' [patent_app_type] => new [patent_app_number] => 10/816307 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13787 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185612.pdf [firstpage_image] =>[orig_patent_app_number] => 10816307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816307
Semiconductor device and process of production of same Mar 31, 2004 Issued
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