
David E. Graybill
Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7086571
[patent_doc_number] => 20050006683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Capacitor and method for fabricating ferroelectric memory device with the same'
[patent_app_type] => utility
[patent_app_number] => 10/899171
[patent_app_country] => US
[patent_app_date] => 2004-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20050006683.pdf
[firstpage_image] =>[orig_patent_app_number] => 10899171
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/899171 | Capacitor and method for fabricating ferroelectric memory device with the same | Jul 26, 2004 | Abandoned |
Array
(
[id] => 7430436
[patent_doc_number] => 20040266223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Laser irradiation method, laser irradiation apparatus, and method of manufacturing a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/896007
[patent_app_country] => US
[patent_app_date] => 2004-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[patent_words_short_claim] => 78
[patent_maintenance] => 1
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[pdf_file] => publications/A1/0266/20040266223.pdf
[firstpage_image] =>[orig_patent_app_number] => 10896007
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/896007 | Laser irradiation method, laser irradiation apparatus, and method of manufacturing a semiconductor device | Jul 21, 2004 | Issued |
| 10/890377 | System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process | Jul 12, 2004 | Abandoned |
Array
(
[id] => 637776
[patent_doc_number] => 07125740
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-24
[patent_title] => 'Solid-state image pickup device and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/889157
[patent_app_country] => US
[patent_app_date] => 2004-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 9203
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[pdf_file] => patents/07/125/07125740.pdf
[firstpage_image] =>[orig_patent_app_number] => 10889157
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/889157 | Solid-state image pickup device and fabrication method thereof | Jul 11, 2004 | Issued |
Array
(
[id] => 5738647
[patent_doc_number] => 20060009038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Processing for overcoming extreme topography'
[patent_app_type] => utility
[patent_app_number] => 10/889437
[patent_app_country] => US
[patent_app_date] => 2004-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 10889437
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/889437 | Processing for overcoming extreme topography | Jul 11, 2004 | Abandoned |
Array
(
[id] => 8027187
[patent_doc_number] => 08142673
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[patent_kind] => B2
[patent_issue_date] => 2012-03-27
[patent_title] => 'Compositions for dissolution of low-k dielectric films, and methods of use'
[patent_app_type] => utility
[patent_app_number] => 10/889597
[patent_app_country] => US
[patent_app_date] => 2004-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/08/142/08142673.pdf
[firstpage_image] =>[orig_patent_app_number] => 10889597
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/889597 | Compositions for dissolution of low-k dielectric films, and methods of use | Jul 11, 2004 | Issued |
Array
(
[id] => 7022575
[patent_doc_number] => 20050016969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'Laser-irradiated metallized electroceramic'
[patent_app_type] => utility
[patent_app_number] => 10/885877
[patent_app_country] => US
[patent_app_date] => 2004-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 10885877
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/885877 | Laser-irradiated metallized electroceramic | Jul 7, 2004 | Issued |
Array
(
[id] => 534110
[patent_doc_number] => 07172930
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[patent_issue_date] => 2007-02-06
[patent_title] => 'Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer'
[patent_app_type] => utility
[patent_app_number] => 10/883887
[patent_app_country] => US
[patent_app_date] => 2004-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3922
[patent_no_of_claims] => 30
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[pdf_file] => patents/07/172/07172930.pdf
[firstpage_image] =>[orig_patent_app_number] => 10883887
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/883887 | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer | Jul 1, 2004 | Issued |
Array
(
[id] => 7061213
[patent_doc_number] => 20050003574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Method of creating a high performance organic semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/884317
[patent_app_country] => US
[patent_app_date] => 2004-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 7995
[patent_no_of_claims] => 42
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[pdf_file] => publications/A1/0003/20050003574.pdf
[firstpage_image] =>[orig_patent_app_number] => 10884317
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/884317 | Method of creating a high performance organic semiconductor device | Jun 30, 2004 | Abandoned |
Array
(
[id] => 432256
[patent_doc_number] => 07265029
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-04
[patent_title] => 'Fabrication of substrates with a useful layer of monocrystalline semiconductor material'
[patent_app_type] => utility
[patent_app_number] => 10/883437
[patent_app_country] => US
[patent_app_date] => 2004-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/07/265/07265029.pdf
[firstpage_image] =>[orig_patent_app_number] => 10883437
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/883437 | Fabrication of substrates with a useful layer of monocrystalline semiconductor material | Jun 30, 2004 | Issued |
Array
(
[id] => 1022563
[patent_doc_number] => 06888229
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Connection components with frangible leads and bus'
[patent_app_type] => utility
[patent_app_number] => 10/872105
[patent_app_country] => US
[patent_app_date] => 2004-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => patents/06/888/06888229.pdf
[firstpage_image] =>[orig_patent_app_number] => 10872105
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/872105 | Connection components with frangible leads and bus | Jun 17, 2004 | Issued |
Array
(
[id] => 766202
[patent_doc_number] => 07008820
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-07
[patent_title] => 'Chip scale package with open substrate'
[patent_app_type] => utility
[patent_app_number] => 10/866561
[patent_app_country] => US
[patent_app_date] => 2004-06-10
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[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/07/008/07008820.pdf
[firstpage_image] =>[orig_patent_app_number] => 10866561
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/866561 | Chip scale package with open substrate | Jun 9, 2004 | Issued |
Array
(
[id] => 7349209
[patent_doc_number] => 20040248401
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Method for forming buried wiring and semiconductor device'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10859217
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/859217 | Method for forming buried wiring and semiconductor device | Jun 2, 2004 | Abandoned |
Array
(
[id] => 7375860
[patent_doc_number] => 20040219763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices'
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[firstpage_image] =>[orig_patent_app_number] => 10855032
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/855032 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices | May 25, 2004 | Issued |
Array
(
[id] => 7429317
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[patent_issue_date] => 2004-10-21
[patent_title] => 'Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof'
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[pdf_file] => publications/A1/0209/20040209453.pdf
[firstpage_image] =>[orig_patent_app_number] => 10847614
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/847614 | Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof | May 17, 2004 | Abandoned |
Array
(
[id] => 721194
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[patent_issue_date] => 2006-05-16
[patent_title] => 'Method and apparatus for adjustably induced biaxial strain'
[patent_app_type] => utility
[patent_app_number] => 10/837027
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[firstpage_image] =>[orig_patent_app_number] => 10837027
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/837027 | Method and apparatus for adjustably induced biaxial strain | Apr 29, 2004 | Issued |
Array
(
[id] => 7184311
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[firstpage_image] =>[orig_patent_app_number] => 10834707
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834707 | Electronic component and fabricating method | Apr 28, 2004 | Abandoned |
Array
(
[id] => 7729357
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[patent_kind] => B2
[patent_issue_date] => 2012-01-24
[patent_title] => 'Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834651 | Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween | Apr 28, 2004 | Issued |
Array
(
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[patent_title] => 'Method for forming die protecting layer'
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[firstpage_image] =>[orig_patent_app_number] => 10818156
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/818156 | Method for forming die protecting layer | Apr 2, 2004 | Abandoned |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 10816307
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/816307 | Semiconductor device and process of production of same | Mar 31, 2004 | Issued |