Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4464051 [patent_doc_number] => 07935565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Electronic devices' [patent_app_type] => utility [patent_app_number] => 10/538857 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10578 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/935/07935565.pdf [firstpage_image] =>[orig_patent_app_number] => 10538857 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/538857
Electronic devices Dec 11, 2003 Issued
Array ( [id] => 1024541 [patent_doc_number] => 06884682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Method for manufacturing flash memory device' [patent_app_type] => utility [patent_app_number] => 10/734533 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2552 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884682.pdf [firstpage_image] =>[orig_patent_app_number] => 10734533 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734533
Method for manufacturing flash memory device Dec 11, 2003 Issued
Array ( [id] => 7471468 [patent_doc_number] => 20040121543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/733233 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2854 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121543.pdf [firstpage_image] =>[orig_patent_app_number] => 10733233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733233
Method of manufacturing semiconductor device Dec 11, 2003 Abandoned
Array ( [id] => 673009 [patent_doc_number] => 07091571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-15 [patent_title] => 'Image sensor package and method for manufacture thereof' [patent_app_type] => utility [patent_app_number] => 10/735184 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091571.pdf [firstpage_image] =>[orig_patent_app_number] => 10735184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735184
Image sensor package and method for manufacture thereof Dec 10, 2003 Issued
Array ( [id] => 7094879 [patent_doc_number] => 20050127482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method of forming a semiconductor package and leadframe therefor' [patent_app_type] => utility [patent_app_number] => 10/729892 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3208 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127482.pdf [firstpage_image] =>[orig_patent_app_number] => 10729892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729892
Method of forming a semiconductor package and leadframe therefor Dec 7, 2003 Issued
Array ( [id] => 710642 [patent_doc_number] => 07056767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Method and apparatus for flip chip device assembly by radiant heating' [patent_app_type] => utility [patent_app_number] => 10/725726 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3154 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/056/07056767.pdf [firstpage_image] =>[orig_patent_app_number] => 10725726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725726
Method and apparatus for flip chip device assembly by radiant heating Dec 1, 2003 Issued
Array ( [id] => 7457196 [patent_doc_number] => 20040119161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Package for housing semiconductor chip, fabrication method thereof and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/724603 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10859 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119161.pdf [firstpage_image] =>[orig_patent_app_number] => 10724603 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724603
Package for housing semiconductor chip, fabrication method thereof and semiconductor device Dec 1, 2003 Abandoned
Array ( [id] => 7024030 [patent_doc_number] => 20050018424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density' [patent_app_type] => utility [patent_app_number] => 10/722672 [patent_app_country] => US [patent_app_date] => 2003-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8237 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20050018424.pdf [firstpage_image] =>[orig_patent_app_number] => 10722672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722672
Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density Nov 27, 2003 Issued
Array ( [id] => 7024030 [patent_doc_number] => 20050018424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density' [patent_app_type] => utility [patent_app_number] => 10/722672 [patent_app_country] => US [patent_app_date] => 2003-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8237 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20050018424.pdf [firstpage_image] =>[orig_patent_app_number] => 10722672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722672
Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density Nov 27, 2003 Issued
Array ( [id] => 7144201 [patent_doc_number] => 20050118764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Forming gate oxides having multiple thicknesses' [patent_app_type] => utility [patent_app_number] => 10/724483 [patent_app_country] => US [patent_app_date] => 2003-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20050118764.pdf [firstpage_image] =>[orig_patent_app_number] => 10724483 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724483
Forming gate oxides having multiple thicknesses Nov 27, 2003 Issued
Array ( [id] => 7800952 [patent_doc_number] => 08129222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'High density chip scale leadframe package and method of manufacturing the package' [patent_app_type] => utility [patent_app_number] => 10/721382 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 7256 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129222.pdf [firstpage_image] =>[orig_patent_app_number] => 10721382 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/721382
High density chip scale leadframe package and method of manufacturing the package Nov 25, 2003 Issued
Array ( [id] => 7300359 [patent_doc_number] => 20040112631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Underfilling material for semiconductor package' [patent_app_type] => new [patent_app_number] => 10/721263 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5782 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20040112631.pdf [firstpage_image] =>[orig_patent_app_number] => 10721263 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/721263
Underfilling material for semiconductor package Nov 25, 2003 Issued
Array ( [id] => 7464772 [patent_doc_number] => 20040095736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Multi-chip package having increased reliabilty' [patent_app_type] => new [patent_app_number] => 10/714801 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3887 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095736.pdf [firstpage_image] =>[orig_patent_app_number] => 10714801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714801
Multi-chip package having increased reliabilty Nov 16, 2003 Abandoned
Array ( [id] => 728384 [patent_doc_number] => 07041569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-09 [patent_title] => 'Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies' [patent_app_type] => utility [patent_app_number] => 10/712067 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4735 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/041/07041569.pdf [firstpage_image] =>[orig_patent_app_number] => 10712067 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712067
Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies Nov 12, 2003 Issued
Array ( [id] => 7408873 [patent_doc_number] => 20040106263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'System and method to reduce noise in a substrate' [patent_app_type] => new [patent_app_number] => 10/706218 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3679 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106263.pdf [firstpage_image] =>[orig_patent_app_number] => 10706218 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706218
System and method to reduce noise in a substrate Nov 11, 2003 Issued
Array ( [id] => 7459135 [patent_doc_number] => 20040094774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Semiconductor light emitting device and method' [patent_app_type] => new [patent_app_number] => 10/705156 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3869 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094774.pdf [firstpage_image] =>[orig_patent_app_number] => 10705156 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705156
Semiconductor light emitting device and method Nov 9, 2003 Issued
Array ( [id] => 7309350 [patent_doc_number] => 20040142574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument' [patent_app_type] => new [patent_app_number] => 10/703573 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5249 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142574.pdf [firstpage_image] =>[orig_patent_app_number] => 10703573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703573
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument Nov 9, 2003 Issued
Array ( [id] => 1028300 [patent_doc_number] => 06881976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Heterojunction BiCMOS semiconductor' [patent_app_type] => utility [patent_app_number] => 10/705163 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/881/06881976.pdf [firstpage_image] =>[orig_patent_app_number] => 10705163 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705163
Heterojunction BiCMOS semiconductor Nov 5, 2003 Issued
Array ( [id] => 570398 [patent_doc_number] => 07465977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Method for producing a packaged integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/532627 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4912 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/465/07465977.pdf [firstpage_image] =>[orig_patent_app_number] => 10532627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/532627
Method for producing a packaged integrated circuit Oct 26, 2003 Issued
Array ( [id] => 509884 [patent_doc_number] => 07196000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method for manufacturing a wafer level chip scale package' [patent_app_type] => utility [patent_app_number] => 10/690782 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 4077 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196000.pdf [firstpage_image] =>[orig_patent_app_number] => 10690782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690782
Method for manufacturing a wafer level chip scale package Oct 20, 2003 Issued
Menu