Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7396990 [patent_doc_number] => 20040104458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Semiconductor deivce and method for manufacturing same' [patent_app_type] => new [patent_app_number] => 10/473723 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4655 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20040104458.pdf [firstpage_image] =>[orig_patent_app_number] => 10473723 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/473723
Semiconductor deivce and method for manufacturing same Sep 30, 2003 Abandoned
Array ( [id] => 7116796 [patent_doc_number] => 20050070097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Atomic laminates for diffusion barrier applications' [patent_app_type] => utility [patent_app_number] => 10/674853 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2994 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070097.pdf [firstpage_image] =>[orig_patent_app_number] => 10674853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674853
Atomic laminates for diffusion barrier applications Sep 28, 2003 Abandoned
Array ( [id] => 946551 [patent_doc_number] => 06964883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Bi-directional silicon controlled rectifier for electrostatic discharge protection' [patent_app_type] => utility [patent_app_number] => 10/670207 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3048 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964883.pdf [firstpage_image] =>[orig_patent_app_number] => 10670207 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670207
Bi-directional silicon controlled rectifier for electrostatic discharge protection Sep 25, 2003 Issued
10/667759 Methods of making thin integrated circuit device packages with improved thermal performance and increased I/O density Sep 21, 2003 Abandoned
Array ( [id] => 779535 [patent_doc_number] => 06995403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Light emitting device' [patent_app_type] => utility [patent_app_number] => 10/655150 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2901 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995403.pdf [firstpage_image] =>[orig_patent_app_number] => 10655150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/655150
Light emitting device Sep 2, 2003 Issued
Array ( [id] => 7260383 [patent_doc_number] => 20040150096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Capping coating for 3D integration applications' [patent_app_type] => new [patent_app_number] => 10/645047 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4785 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150096.pdf [firstpage_image] =>[orig_patent_app_number] => 10645047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/645047
Capping coating for 3D integration applications Aug 20, 2003 Abandoned
Array ( [id] => 7313571 [patent_doc_number] => 20040033644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Methods for transfer molding encapsulation of a semiconductor die with attached heat sink' [patent_app_type] => new [patent_app_number] => 10/639127 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3135 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033644.pdf [firstpage_image] =>[orig_patent_app_number] => 10639127 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/639127
Methods for transfer molding encapsulation of a semiconductor die with attached heat sink Aug 11, 2003 Abandoned
Array ( [id] => 7368974 [patent_doc_number] => 20040026792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Flip-chip package with underfill having low density filler' [patent_app_type] => new [patent_app_number] => 10/635774 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5359 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20040026792.pdf [firstpage_image] =>[orig_patent_app_number] => 10635774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635774
Flip-chip package with underfill having low density filler Aug 5, 2003 Issued
Array ( [id] => 7184210 [patent_doc_number] => 20040203216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => '[FABRICATION METHOD FOR SHALLOW TRENCH ISOLATION REGION]' [patent_app_type] => new [patent_app_number] => 10/604615 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20040203216.pdf [firstpage_image] =>[orig_patent_app_number] => 10604615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604615
Fabrication method for shallow trench isolation region Aug 4, 2003 Issued
Array ( [id] => 968452 [patent_doc_number] => 06939726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Via array monitor and method of monitoring induced electrical charging' [patent_app_type] => utility [patent_app_number] => 10/634005 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/939/06939726.pdf [firstpage_image] =>[orig_patent_app_number] => 10634005 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634005
Via array monitor and method of monitoring induced electrical charging Aug 3, 2003 Issued
Array ( [id] => 991109 [patent_doc_number] => 06919636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-19 [patent_title] => 'Interconnects with a dielectric sealant layer' [patent_app_type] => utility [patent_app_number] => 10/630809 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3620 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919636.pdf [firstpage_image] =>[orig_patent_app_number] => 10630809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630809
Interconnects with a dielectric sealant layer Jul 30, 2003 Issued
Array ( [id] => 7148010 [patent_doc_number] => 20050023682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'High reliability chip scale package' [patent_app_type] => utility [patent_app_number] => 10/631083 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2830 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023682.pdf [firstpage_image] =>[orig_patent_app_number] => 10631083 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631083
High reliability chip scale package Jul 30, 2003 Abandoned
Array ( [id] => 7150522 [patent_doc_number] => 20050024839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Ball grid array package' [patent_app_type] => utility [patent_app_number] => 10/631569 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3891 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024839.pdf [firstpage_image] =>[orig_patent_app_number] => 10631569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631569
Ball grid array package Jul 30, 2003 Issued
Array ( [id] => 7025649 [patent_doc_number] => 20050020043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Methods for reducing cell pitch in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/627115 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3787 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20050020043.pdf [firstpage_image] =>[orig_patent_app_number] => 10627115 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627115
Methods for reducing cell pitch in semiconductor devices Jul 24, 2003 Abandoned
Array ( [id] => 6987646 [patent_doc_number] => 20050087138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Semiconductor device manufacturing apparatus and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/626233 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6750 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20050087138.pdf [firstpage_image] =>[orig_patent_app_number] => 10626233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626233
Semiconductor device manufacturing apparatus and semiconductor device manufacturing method Jul 23, 2003 Issued
Array ( [id] => 7297625 [patent_doc_number] => 20040125515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density' [patent_app_type] => new [patent_app_number] => 10/625185 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8303 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20040125515.pdf [firstpage_image] =>[orig_patent_app_number] => 10625185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625185
Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density Jul 22, 2003 Issued
Array ( [id] => 1046734 [patent_doc_number] => 06864128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Manufacturing method for a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/623563 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10963 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864128.pdf [firstpage_image] =>[orig_patent_app_number] => 10623563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/623563
Manufacturing method for a semiconductor device Jul 21, 2003 Issued
Array ( [id] => 7398918 [patent_doc_number] => 20040018704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Multirate circular buffer and method of operating the same' [patent_app_type] => new [patent_app_number] => 10/622612 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4266 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20040018704.pdf [firstpage_image] =>[orig_patent_app_number] => 10622612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622612
Multirate circular buffer and method of operating the same Jul 16, 2003 Abandoned
Array ( [id] => 7675171 [patent_doc_number] => 20040126947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'pMOS device having ultra shallow super-steep-retrograde epi-channel with dual channel doping and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/616625 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5253 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20040126947.pdf [firstpage_image] =>[orig_patent_app_number] => 10616625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/616625
pMOS device having ultra shallow super-steep-retrograde epi-channel with dual channel doping and method for fabricating the same Jul 9, 2003 Issued
Array ( [id] => 1104687 [patent_doc_number] => 06812042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Capacitor and method for fabricating ferroelectric memory device with the same' [patent_app_type] => B2 [patent_app_number] => 10/613993 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4145 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812042.pdf [firstpage_image] =>[orig_patent_app_number] => 10613993 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/613993
Capacitor and method for fabricating ferroelectric memory device with the same Jul 7, 2003 Issued
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