Search

David E. Graybill

Examiner (ID: 12341, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 3727, 2812, 1107, 2827, 2814, 1763, 2822
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6809182 [patent_doc_number] => 20030199121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Wafer scale thin film package' [patent_app_type] => new [patent_app_number] => 10/438947 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2943 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20030199121.pdf [firstpage_image] =>[orig_patent_app_number] => 10438947 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438947
Wafer scale thin film package May 14, 2003 Issued
Array ( [id] => 6795605 [patent_doc_number] => 20030174478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Ball grid array module' [patent_app_type] => new [patent_app_number] => 10/431177 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2995 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20030174478.pdf [firstpage_image] =>[orig_patent_app_number] => 10431177 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431177
Ball grid array module May 7, 2003 Issued
Array ( [id] => 712265 [patent_doc_number] => 07057265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Semiconductor device and process for fabrication thereof' [patent_app_type] => utility [patent_app_number] => 10/428126 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7953 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057265.pdf [firstpage_image] =>[orig_patent_app_number] => 10428126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428126
Semiconductor device and process for fabrication thereof May 1, 2003 Issued
Array ( [id] => 6738281 [patent_doc_number] => 20030155649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Double-packaged multi-chip semiconductor module' [patent_app_type] => new [patent_app_number] => 10/423122 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3165 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20030155649.pdf [firstpage_image] =>[orig_patent_app_number] => 10423122 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/423122
Double-packaged multi-chip semiconductor module Apr 24, 2003 Issued
Array ( [id] => 6847147 [patent_doc_number] => 20030166314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Resin encapsulated BGA-type semiconductor device' [patent_app_type] => new [patent_app_number] => 10/412001 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4108 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20030166314.pdf [firstpage_image] =>[orig_patent_app_number] => 10412001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/412001
Resin encapsulated BGA-type semiconductor device Apr 10, 2003 Abandoned
Array ( [id] => 6948725 [patent_doc_number] => 20050223819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Method and a device for measuring stress forces in refiners' [patent_app_type] => utility [patent_app_number] => 10/509981 [patent_app_country] => US [patent_app_date] => 2003-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5184 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223819.pdf [firstpage_image] =>[orig_patent_app_number] => 10509981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/509981
Method and a device for measuring stress forces in refiners Apr 1, 2003 Abandoned
Array ( [id] => 7398921 [patent_doc_number] => 20040018705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Semiconductor structure and method for processing such a structure' [patent_app_type] => new [patent_app_number] => 10/403463 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4266 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20040018705.pdf [firstpage_image] =>[orig_patent_app_number] => 10403463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/403463
Semiconductor structure and method for processing such a structure Mar 30, 2003 Abandoned
Array ( [id] => 658076 [patent_doc_number] => 07105380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Method of temporarily securing a die to a burn-in carrier' [patent_app_type] => utility [patent_app_number] => 10/395477 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105380.pdf [firstpage_image] =>[orig_patent_app_number] => 10395477 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/395477
Method of temporarily securing a die to a burn-in carrier Mar 23, 2003 Issued
Array ( [id] => 7045656 [patent_doc_number] => 20050250251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Method and apparatus for decoupling conductive portions of a microelectronic device package' [patent_app_type] => utility [patent_app_number] => 10/393376 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3844 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250251.pdf [firstpage_image] =>[orig_patent_app_number] => 10393376 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/393376
Method and apparatus for decoupling conductive portions of a microelectronic device package Mar 18, 2003 Issued
Array ( [id] => 6704390 [patent_doc_number] => 20030151124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/385555 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5890 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151124.pdf [firstpage_image] =>[orig_patent_app_number] => 10385555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/385555
Integrated circuit device Mar 10, 2003 Issued
Array ( [id] => 415227 [patent_doc_number] => 07279410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-09 [patent_title] => 'Method for forming inlaid structures for IC interconnections' [patent_app_type] => utility [patent_app_number] => 10/379757 [patent_app_country] => US [patent_app_date] => 2003-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 5683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279410.pdf [firstpage_image] =>[orig_patent_app_number] => 10379757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379757
Method for forming inlaid structures for IC interconnections Mar 4, 2003 Issued
Array ( [id] => 6805067 [patent_doc_number] => 20030232461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Methods for packaging image sensitive electronic devices' [patent_app_type] => new [patent_app_number] => 10/370674 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3896 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20030232461.pdf [firstpage_image] =>[orig_patent_app_number] => 10370674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/370674
Methods for packaging image sensitive electronic devices Feb 20, 2003 Issued
Array ( [id] => 6834398 [patent_doc_number] => 20030161943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug' [patent_app_type] => new [patent_app_number] => 10/367214 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4060 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161943.pdf [firstpage_image] =>[orig_patent_app_number] => 10367214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/367214
Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug Feb 12, 2003 Issued
Array ( [id] => 1083478 [patent_doc_number] => 06833609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-21 [patent_title] => 'Integrated circuit device packages and substrates for making the packages' [patent_app_type] => B1 [patent_app_number] => 10/354772 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 6625 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833609.pdf [firstpage_image] =>[orig_patent_app_number] => 10354772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/354772
Integrated circuit device packages and substrates for making the packages Jan 29, 2003 Issued
Array ( [id] => 1095860 [patent_doc_number] => 06821815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of assembling a semiconductor chip package' [patent_app_type] => B2 [patent_app_number] => 10/353737 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7814 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821815.pdf [firstpage_image] =>[orig_patent_app_number] => 10353737 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353737
Method of assembling a semiconductor chip package Jan 28, 2003 Issued
Array ( [id] => 7283654 [patent_doc_number] => 20040145045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Bonding pad and via structure design' [patent_app_type] => new [patent_app_number] => 10/353554 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3731 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145045.pdf [firstpage_image] =>[orig_patent_app_number] => 10353554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353554
Bonding pad and via structure design Jan 28, 2003 Issued
Array ( [id] => 6627915 [patent_doc_number] => 20030102551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Semiconductor device and method for manufacturing' [patent_app_type] => new [patent_app_number] => 10/331480 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6653 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20030102551.pdf [firstpage_image] =>[orig_patent_app_number] => 10331480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331480
Semiconductor device and method for manufacturing Dec 30, 2002 Issued
Array ( [id] => 1107542 [patent_doc_number] => 06808953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Gap tuning for surface micromachined structures in an epitaxial reactor' [patent_app_type] => B2 [patent_app_number] => 10/334463 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2939 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808953.pdf [firstpage_image] =>[orig_patent_app_number] => 10334463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334463
Gap tuning for surface micromachined structures in an epitaxial reactor Dec 30, 2002 Issued
Array ( [id] => 693980 [patent_doc_number] => 07070831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Member for semiconductor package and semiconductor package using the same, and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 10/330202 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2459 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/070/07070831.pdf [firstpage_image] =>[orig_patent_app_number] => 10330202 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330202
Member for semiconductor package and semiconductor package using the same, and fabrication method thereof Dec 29, 2002 Issued
Array ( [id] => 5843605 [patent_doc_number] => 20060121690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Three-dimensional device fabrication method' [patent_app_type] => utility [patent_app_number] => 10/538905 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 4638 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20060121690.pdf [firstpage_image] =>[orig_patent_app_number] => 10538905 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/538905
Three-dimensional device fabrication method Dec 19, 2002 Issued
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