
David E. Graybill
Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814 |
| Total Applications | 1844 |
| Issued Applications | 1278 |
| Pending Applications | 38 |
| Abandoned Applications | 533 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7058917
[patent_doc_number] => 20050001276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Selective etching of silicon carbide films'
[patent_app_type] => utility
[patent_app_number] => 10/613508
[patent_app_country] => US
[patent_app_date] => 2003-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2823
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20050001276.pdf
[firstpage_image] =>[orig_patent_app_number] => 10613508
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/613508 | Selective etching of silicon carbide films | Jul 2, 2003 | Issued |
Array
(
[id] => 7353365
[patent_doc_number] => 20040003496
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-08
[patent_title] => 'Interposer to couple a microelectronic device package to a circuit board'
[patent_app_type] => new
[patent_app_number] => 10/612544
[patent_app_country] => US
[patent_app_date] => 2003-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3050
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20040003496.pdf
[firstpage_image] =>[orig_patent_app_number] => 10612544
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/612544 | Interposer to couple a microelectronic device package to a circuit board | Jun 30, 2003 | Abandoned |
Array
(
[id] => 7328860
[patent_doc_number] => 20040253767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-16
[patent_title] => 'Thermally enhanced component substrate'
[patent_app_type] => new
[patent_app_number] => 10/459140
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4619
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20040253767.pdf
[firstpage_image] =>[orig_patent_app_number] => 10459140
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/459140 | Thermally enhanced component substrate | Jun 9, 2003 | Issued |
Array
(
[id] => 7135208
[patent_doc_number] => 20040043603
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Semiconductor component with backside contacts and method of fabrication'
[patent_app_type] => new
[patent_app_number] => 10/457774
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6629
[patent_no_of_claims] => 63
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20040043603.pdf
[firstpage_image] =>[orig_patent_app_number] => 10457774
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/457774 | Semiconductor component with backside contacts and method of fabrication | Jun 9, 2003 | Issued |
Array
(
[id] => 762039
[patent_doc_number] => 07012314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-14
[patent_title] => 'Semiconductor devices with reduced active region defects and unique contacting schemes'
[patent_app_type] => utility
[patent_app_number] => 10/453037
[patent_app_country] => US
[patent_app_date] => 2003-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 29
[patent_no_of_words] => 13361
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/012/07012314.pdf
[firstpage_image] =>[orig_patent_app_number] => 10453037
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/453037 | Semiconductor devices with reduced active region defects and unique contacting schemes | Jun 2, 2003 | Issued |
Array
(
[id] => 6809182
[patent_doc_number] => 20030199121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Wafer scale thin film package'
[patent_app_type] => new
[patent_app_number] => 10/438947
[patent_app_country] => US
[patent_app_date] => 2003-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2943
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20030199121.pdf
[firstpage_image] =>[orig_patent_app_number] => 10438947
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/438947 | Wafer scale thin film package | May 14, 2003 | Issued |
Array
(
[id] => 6795605
[patent_doc_number] => 20030174478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-18
[patent_title] => 'Ball grid array module'
[patent_app_type] => new
[patent_app_number] => 10/431177
[patent_app_country] => US
[patent_app_date] => 2003-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2995
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20030174478.pdf
[firstpage_image] =>[orig_patent_app_number] => 10431177
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/431177 | Ball grid array module | May 7, 2003 | Issued |
Array
(
[id] => 712265
[patent_doc_number] => 07057265
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-06
[patent_title] => 'Semiconductor device and process for fabrication thereof'
[patent_app_type] => utility
[patent_app_number] => 10/428126
[patent_app_country] => US
[patent_app_date] => 2003-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 7953
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/057/07057265.pdf
[firstpage_image] =>[orig_patent_app_number] => 10428126
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/428126 | Semiconductor device and process for fabrication thereof | May 1, 2003 | Issued |
Array
(
[id] => 6738281
[patent_doc_number] => 20030155649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-21
[patent_title] => 'Double-packaged multi-chip semiconductor module'
[patent_app_type] => new
[patent_app_number] => 10/423122
[patent_app_country] => US
[patent_app_date] => 2003-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3165
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20030155649.pdf
[firstpage_image] =>[orig_patent_app_number] => 10423122
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/423122 | Double-packaged multi-chip semiconductor module | Apr 24, 2003 | Issued |
Array
(
[id] => 6847147
[patent_doc_number] => 20030166314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-04
[patent_title] => 'Resin encapsulated BGA-type semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/412001
[patent_app_country] => US
[patent_app_date] => 2003-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4108
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0166/20030166314.pdf
[firstpage_image] =>[orig_patent_app_number] => 10412001
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/412001 | Resin encapsulated BGA-type semiconductor device | Apr 10, 2003 | Abandoned |
Array
(
[id] => 6948725
[patent_doc_number] => 20050223819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Method and a device for measuring stress forces in refiners'
[patent_app_type] => utility
[patent_app_number] => 10/509981
[patent_app_country] => US
[patent_app_date] => 2003-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5184
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20050223819.pdf
[firstpage_image] =>[orig_patent_app_number] => 10509981
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/509981 | Method and a device for measuring stress forces in refiners | Apr 1, 2003 | Abandoned |
Array
(
[id] => 7398921
[patent_doc_number] => 20040018705
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Semiconductor structure and method for processing such a structure'
[patent_app_type] => new
[patent_app_number] => 10/403463
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4266
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20040018705.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403463
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403463 | Semiconductor structure and method for processing such a structure | Mar 30, 2003 | Abandoned |
Array
(
[id] => 658076
[patent_doc_number] => 07105380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Method of temporarily securing a die to a burn-in carrier'
[patent_app_type] => utility
[patent_app_number] => 10/395477
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2787
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/105/07105380.pdf
[firstpage_image] =>[orig_patent_app_number] => 10395477
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395477 | Method of temporarily securing a die to a burn-in carrier | Mar 23, 2003 | Issued |
Array
(
[id] => 7045656
[patent_doc_number] => 20050250251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-10
[patent_title] => 'Method and apparatus for decoupling conductive portions of a microelectronic device package'
[patent_app_type] => utility
[patent_app_number] => 10/393376
[patent_app_country] => US
[patent_app_date] => 2003-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3844
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20050250251.pdf
[firstpage_image] =>[orig_patent_app_number] => 10393376
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/393376 | Method and apparatus for decoupling conductive portions of a microelectronic device package | Mar 18, 2003 | Issued |
Array
(
[id] => 6704390
[patent_doc_number] => 20030151124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-14
[patent_title] => 'Integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 10/385555
[patent_app_country] => US
[patent_app_date] => 2003-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 5890
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 9
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20030151124.pdf
[firstpage_image] =>[orig_patent_app_number] => 10385555
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/385555 | Integrated circuit device | Mar 10, 2003 | Issued |
Array
(
[id] => 415227
[patent_doc_number] => 07279410
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-09
[patent_title] => 'Method for forming inlaid structures for IC interconnections'
[patent_app_type] => utility
[patent_app_number] => 10/379757
[patent_app_country] => US
[patent_app_date] => 2003-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 5683
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/279/07279410.pdf
[firstpage_image] =>[orig_patent_app_number] => 10379757
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/379757 | Method for forming inlaid structures for IC interconnections | Mar 4, 2003 | Issued |
Array
(
[id] => 6805067
[patent_doc_number] => 20030232461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-18
[patent_title] => 'Methods for packaging image sensitive electronic devices'
[patent_app_type] => new
[patent_app_number] => 10/370674
[patent_app_country] => US
[patent_app_date] => 2003-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3896
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20030232461.pdf
[firstpage_image] =>[orig_patent_app_number] => 10370674
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/370674 | Methods for packaging image sensitive electronic devices | Feb 20, 2003 | Issued |
Array
(
[id] => 6834398
[patent_doc_number] => 20030161943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug'
[patent_app_type] => new
[patent_app_number] => 10/367214
[patent_app_country] => US
[patent_app_date] => 2003-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4060
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20030161943.pdf
[firstpage_image] =>[orig_patent_app_number] => 10367214
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/367214 | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug | Feb 12, 2003 | Issued |
Array
(
[id] => 1083478
[patent_doc_number] => 06833609
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-21
[patent_title] => 'Integrated circuit device packages and substrates for making the packages'
[patent_app_type] => B1
[patent_app_number] => 10/354772
[patent_app_country] => US
[patent_app_date] => 2003-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 25
[patent_no_of_words] => 6625
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/833/06833609.pdf
[firstpage_image] =>[orig_patent_app_number] => 10354772
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/354772 | Integrated circuit device packages and substrates for making the packages | Jan 29, 2003 | Issued |
Array
(
[id] => 1095860
[patent_doc_number] => 06821815
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-23
[patent_title] => 'Method of assembling a semiconductor chip package'
[patent_app_type] => B2
[patent_app_number] => 10/353737
[patent_app_country] => US
[patent_app_date] => 2003-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 7814
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/821/06821815.pdf
[firstpage_image] =>[orig_patent_app_number] => 10353737
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/353737 | Method of assembling a semiconductor chip package | Jan 28, 2003 | Issued |