Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6393649 [patent_doc_number] => 20020036100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Microbeam assembly for integrated circuit interconnection to substrates' [patent_app_type] => new [patent_app_number] => 10/005633 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4414 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036100.pdf [firstpage_image] =>[orig_patent_app_number] => 10005633 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005633
Microbeam assembly for integrated circuit interconnection to substrates Dec 4, 2001 Abandoned
Array ( [id] => 935675 [patent_doc_number] => 06975025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Semiconductor chip package and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 09/999169 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3010 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975025.pdf [firstpage_image] =>[orig_patent_app_number] => 09999169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999169
Semiconductor chip package and method of manufacturing same Dec 2, 2001 Issued
Array ( [id] => 6095905 [patent_doc_number] => 20020052091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Automated combi deposition apparatus and method' [patent_app_type] => new [patent_app_number] => 09/994669 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3223 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052091.pdf [firstpage_image] =>[orig_patent_app_number] => 09994669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994669
Automated combi deposition apparatus and method Nov 27, 2001 Issued
Array ( [id] => 1310158 [patent_doc_number] => 06617672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method for producing contact chip cards with a low-cost dielectric' [patent_app_type] => B1 [patent_app_number] => 09/979709 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 0 [patent_no_of_words] => 3372 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617672.pdf [firstpage_image] =>[orig_patent_app_number] => 09979709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/979709
Method for producing contact chip cards with a low-cost dielectric Nov 25, 2001 Issued
Array ( [id] => 1192905 [patent_doc_number] => 06730543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Methods for multiple die stack apparatus employing' [patent_app_type] => B2 [patent_app_number] => 09/989341 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3769 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730543.pdf [firstpage_image] =>[orig_patent_app_number] => 09989341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989341
Methods for multiple die stack apparatus employing Nov 19, 2001 Issued
Array ( [id] => 999872 [patent_doc_number] => 06911723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Multiple die stack apparatus employing T-shaped interposer elements' [patent_app_type] => utility [patent_app_number] => 09/989326 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3769 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911723.pdf [firstpage_image] =>[orig_patent_app_number] => 09989326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989326
Multiple die stack apparatus employing T-shaped interposer elements Nov 19, 2001 Issued
Array ( [id] => 5828670 [patent_doc_number] => 20020068381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Ultra-fine contact alignment' [patent_app_type] => new [patent_app_number] => 09/985693 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4646 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20020068381.pdf [firstpage_image] =>[orig_patent_app_number] => 09985693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/985693
Ultra-fine contact alignment Nov 4, 2001 Abandoned
Array ( [id] => 5918104 [patent_doc_number] => 20020113322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Semiconductor device and method to produce the same' [patent_app_type] => new [patent_app_number] => 10/000177 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10380 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113322.pdf [firstpage_image] =>[orig_patent_app_number] => 10000177 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/000177
Semiconductor device and method to produce the same Nov 1, 2001 Abandoned
09/806401 Electronic module, especially a multichip module, with multi-layer metallization and corresponding production method Oct 21, 2001 Abandoned
Array ( [id] => 6573317 [patent_doc_number] => 20020014699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Semiconductor device, function setting method thereof, and evaluation method thereof' [patent_app_type] => new [patent_app_number] => 09/968898 [patent_app_country] => US [patent_app_date] => 2001-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11791 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014699.pdf [firstpage_image] =>[orig_patent_app_number] => 09968898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968898
Semiconductor device, function setting method thereof, and evaluation method thereof Oct 2, 2001 Issued
Array ( [id] => 7604953 [patent_doc_number] => 07115977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Multi-chip package type semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/963590 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3985 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115977.pdf [firstpage_image] =>[orig_patent_app_number] => 09963590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/963590
Multi-chip package type semiconductor device Sep 26, 2001 Issued
Array ( [id] => 675673 [patent_doc_number] => 07087442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Process for the formation of a spatial chip arrangement and spatial chip arrangement' [patent_app_type] => utility [patent_app_number] => 09/962553 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3974 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087442.pdf [firstpage_image] =>[orig_patent_app_number] => 09962553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962553
Process for the formation of a spatial chip arrangement and spatial chip arrangement Sep 23, 2001 Issued
Array ( [id] => 6395981 [patent_doc_number] => 20020036345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'High frequency flip chip module and assembling method thereof' [patent_app_type] => new [patent_app_number] => 09/960338 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036345.pdf [firstpage_image] =>[orig_patent_app_number] => 09960338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/960338
High frequency flip chip module and assembling method thereof Sep 23, 2001 Abandoned
Array ( [id] => 6129997 [patent_doc_number] => 20020076852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Method for manufacturing a component which is encapsulated in plastic, and a component which is encapsulated in plastic' [patent_app_type] => new [patent_app_number] => 09/962697 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3089 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20020076852.pdf [firstpage_image] =>[orig_patent_app_number] => 09962697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962697
Method for manufacturing a component which is encapsulated in plastic, and a component which is encapsulated in plastic Sep 23, 2001 Abandoned
Array ( [id] => 6237537 [patent_doc_number] => 20020043702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Semiconductor package comprising substrate with mounting leads and manufacturing method therefor' [patent_app_type] => new [patent_app_number] => 09/957888 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2990 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043702.pdf [firstpage_image] =>[orig_patent_app_number] => 09957888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957888
Semiconductor package comprising substrate with mounting leads and manufacturing method therefor Sep 19, 2001 Abandoned
Array ( [id] => 6720894 [patent_doc_number] => 20030054583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Method for producing an image sensor assembly' [patent_app_type] => new [patent_app_number] => 09/957188 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1225 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054583.pdf [firstpage_image] =>[orig_patent_app_number] => 09957188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957188
Method for producing an image sensor assembly Sep 19, 2001 Abandoned
Array ( [id] => 1022433 [patent_doc_number] => 06888158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Bare chip carrier and method for manufacturing semiconductor device using the bare chip carrier' [patent_app_type] => utility [patent_app_number] => 09/956348 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3295 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888158.pdf [firstpage_image] =>[orig_patent_app_number] => 09956348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956348
Bare chip carrier and method for manufacturing semiconductor device using the bare chip carrier Sep 19, 2001 Issued
Array ( [id] => 1576417 [patent_doc_number] => 06469383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Flip-chip transition interface structure' [patent_app_type] => B1 [patent_app_number] => 09/957439 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6386 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469383.pdf [firstpage_image] =>[orig_patent_app_number] => 09957439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957439
Flip-chip transition interface structure Sep 16, 2001 Issued
Array ( [id] => 6577680 [patent_doc_number] => 20020041015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Semiconductor chip, semiconductor device, methods of fabricating thereof, circuit board and electronic device' [patent_app_type] => new [patent_app_number] => 09/948943 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12136 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041015.pdf [firstpage_image] =>[orig_patent_app_number] => 09948943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948943
Semiconductor chip, semiconductor device, methods of fabricating thereof, circuit board and electronic device Sep 6, 2001 Issued
Array ( [id] => 757552 [patent_doc_number] => 07015066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly' [patent_app_type] => utility [patent_app_number] => 09/946995 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4747 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015066.pdf [firstpage_image] =>[orig_patent_app_number] => 09946995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946995
Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly Sep 4, 2001 Issued
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