Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13215009 [patent_doc_number] => 10121882 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => Gate line plug structures for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 15/859353 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859353
Gate line plug structures for advanced integrated circuit structure fabrication Dec 29, 2017 Issued
Array ( [id] => 14382437 [patent_doc_number] => 20190165131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 15/859352 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859352
Gate cut and fin trim isolation for advanced integrated circuit structure fabrication Dec 29, 2017 Issued
Array ( [id] => 14382111 [patent_doc_number] => 20190164968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => DIFFERENTIATED VOLTAGE THRESHOLD METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 15/859355 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 75740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859355
Differentiated voltage threshold metal gate structures for advanced integrated circuit structure fabrication Dec 29, 2017 Issued
Array ( [id] => 16202133 [patent_doc_number] => 10727313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Dual metal gate structures for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 15/859356 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73769 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859356
Dual metal gate structures for advanced integrated circuit structure fabrication Dec 29, 2017 Issued
Array ( [id] => 13214995 [patent_doc_number] => 10121875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => Replacement gate structures for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 15/859354 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73772 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859354 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859354
Replacement gate structures for advanced integrated circuit structure fabrication Dec 29, 2017 Issued
Array ( [id] => 15984991 [patent_doc_number] => 10672835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Thermal insulation for three-dimensional memory arrays [patent_app_type] => utility [patent_app_number] => 15/855669 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11217 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855669 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855669
Thermal insulation for three-dimensional memory arrays Dec 26, 2017 Issued
Array ( [id] => 16464217 [patent_doc_number] => 10847580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Thermal insulation for three-dimensional memory arrays [patent_app_type] => utility [patent_app_number] => 15/855666 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11218 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855666
Thermal insulation for three-dimensional memory arrays Dec 26, 2017 Issued
Array ( [id] => 12631785 [patent_doc_number] => 20180102425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => III-NITRIDE TRANSISTOR INCLUDING A III-N DEPLETING LAYER [patent_app_type] => utility [patent_app_number] => 15/836157 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836157
III-Nitride transistor including a III-N depleting layer Dec 7, 2017 Issued
Array ( [id] => 14268273 [patent_doc_number] => 10283709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/824999 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 7823 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824999 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824999
Semiconductor device and method of manufacturing the same Nov 27, 2017 Issued
Array ( [id] => 12802207 [patent_doc_number] => 20180159239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => LOW LOSS ELECTRICAL TRANSMISSION MECHANISM AND ANTENNA USING SAME [patent_app_type] => utility [patent_app_number] => 15/824996 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824996 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824996
LOW LOSS ELECTRICAL TRANSMISSION MECHANISM AND ANTENNA USING SAME Nov 27, 2017 Abandoned
Array ( [id] => 14381743 [patent_doc_number] => 20190164784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => DIE SEPARATION USING ADHESIVE-LAYER LASER SCRIBING [patent_app_type] => utility [patent_app_number] => 15/825079 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825079
Die separation using adhesive-layer laser scribing Nov 27, 2017 Issued
Array ( [id] => 12801331 [patent_doc_number] => 20180158946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/800870 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800870 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800870
Semiconductor device and method of manufacturing semiconductor device Oct 31, 2017 Issued
Array ( [id] => 13058231 [patent_doc_number] => 10050524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => Circuit for level shifting a clock signal using a voltage multiplier [patent_app_type] => utility [patent_app_number] => 15/800896 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 6430 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800896 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800896
Circuit for level shifting a clock signal using a voltage multiplier Oct 31, 2017 Issued
Array ( [id] => 12738811 [patent_doc_number] => 20180138104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => THERMAL VIA ARRANGEMENT FOR MULTI-CHANNEL SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/800611 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800611
Thermal via arrangement for multi-channel semiconductor device Oct 31, 2017 Issued
Array ( [id] => 14238563 [patent_doc_number] => 20190131454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SEMICONDUCTOR DEVICE WITH STRAINED SILICON LAYERS ON POROUS SILICON [patent_app_type] => utility [patent_app_number] => 15/800916 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800916 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800916
SEMICONDUCTOR DEVICE WITH STRAINED SILICON LAYERS ON POROUS SILICON Oct 31, 2017 Abandoned
Array ( [id] => 13950855 [patent_doc_number] => 10211206 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-19 [patent_title] => Two-port vertical SRAM circuit structure and method for producing the same [patent_app_type] => utility [patent_app_number] => 15/800905 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6396 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800905 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800905
Two-port vertical SRAM circuit structure and method for producing the same Oct 31, 2017 Issued
Array ( [id] => 16516026 [patent_doc_number] => 20200395284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/630703 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630703 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/630703
Semiconductor device and method of manufacturing semiconductor device Oct 25, 2017 Issued
Array ( [id] => 14875701 [patent_doc_number] => 20190288092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/344177 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16344177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/344177
Method for manufacturing semiconductor device Oct 24, 2017 Issued
Array ( [id] => 14050339 [patent_doc_number] => 20190081277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => OLED DISPLAY PANEL PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 15/571026 [patent_app_country] => US [patent_app_date] => 2017-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/571026
OLED DISPLAY PANEL PACKAGING METHOD Oct 18, 2017 Abandoned
Array ( [id] => 17456262 [patent_doc_number] => 11271129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Surface treatment of solar cells [patent_app_type] => utility [patent_app_number] => 16/344176 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4056 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16344176 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/344176
Surface treatment of solar cells Oct 16, 2017 Issued
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