Search

David E. Graybill

Examiner (ID: 16212, Phone: (571)272-1930 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2827, 1763, 2812, 3727, 1107, 2822, 2814
Total Applications
1844
Issued Applications
1278
Pending Applications
38
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1162890 [patent_doc_number] => 06759266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Quick sealing glass-lidded package fabrication method' [patent_app_type] => B1 [patent_app_number] => 09/946861 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5401 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759266.pdf [firstpage_image] =>[orig_patent_app_number] => 09946861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946861
Quick sealing glass-lidded package fabrication method Sep 3, 2001 Issued
Array ( [id] => 6107203 [patent_doc_number] => 20020171138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Multilayer wiring board and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/943512 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6394 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171138.pdf [firstpage_image] =>[orig_patent_app_number] => 09943512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943512
Multilayer wiring board and semiconductor device Aug 30, 2001 Abandoned
Array ( [id] => 7036888 [patent_doc_number] => 20050156322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Thin semiconductor package including stacked dies' [patent_app_type] => utility [patent_app_number] => 09/944732 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7475 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156322.pdf [firstpage_image] =>[orig_patent_app_number] => 09944732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944732
Thin semiconductor package including stacked dies Aug 30, 2001 Abandoned
Array ( [id] => 1092744 [patent_doc_number] => 06825055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Method for assembling integral type electronic component and integral type electronic component' [patent_app_type] => B2 [patent_app_number] => 09/940876 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2421 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825055.pdf [firstpage_image] =>[orig_patent_app_number] => 09940876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940876
Method for assembling integral type electronic component and integral type electronic component Aug 28, 2001 Issued
Array ( [id] => 6476717 [patent_doc_number] => 20020024127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Semiconductor device and manufacture method of that' [patent_app_type] => new [patent_app_number] => 09/939669 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 14100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024127.pdf [firstpage_image] =>[orig_patent_app_number] => 09939669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939669
Semiconductor device and manufacture method of that Aug 27, 2001 Issued
Array ( [id] => 6694935 [patent_doc_number] => 20030107129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Resin encapsulated BGA-type semiconductor device' [patent_app_type] => new [patent_app_number] => 09/940249 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4108 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107129.pdf [firstpage_image] =>[orig_patent_app_number] => 09940249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940249
Resin encapsulated BGA-type semiconductor device Aug 26, 2001 Abandoned
Array ( [id] => 6690924 [patent_doc_number] => 20030038356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods' [patent_app_type] => new [patent_app_number] => 09/939258 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6037 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038356.pdf [firstpage_image] =>[orig_patent_app_number] => 09939258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939258
Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods Aug 23, 2001 Abandoned
Array ( [id] => 5814872 [patent_doc_number] => 20020039811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'A method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/934651 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9955 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20020039811.pdf [firstpage_image] =>[orig_patent_app_number] => 09934651 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/934651
A method of manufacturing a semiconductor device Aug 22, 2001 Abandoned
Array ( [id] => 6845387 [patent_doc_number] => 20030164554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Quad flat no lead (QFN) grid array package, method of making and memory module and computer system including same' [patent_app_type] => new [patent_app_number] => 09/933297 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4364 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20030164554.pdf [firstpage_image] =>[orig_patent_app_number] => 09933297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933297
Quad flat no lead (QFN) grid array package, method of making and memory module and computer system including same Aug 19, 2001 Issued
Array ( [id] => 5888746 [patent_doc_number] => 20020013065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Wafer processing apparatus and method, wafer convey robot, semiconductor substrate fabrication method, and semiconductor fabrication apparatus' [patent_app_type] => new [patent_app_number] => 09/931771 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7632 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013065.pdf [firstpage_image] =>[orig_patent_app_number] => 09931771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931771
Wafer processing apparatus and method, wafer convey robot, semiconductor substrate fabrication method, and semiconductor fabrication apparatus Aug 19, 2001 Abandoned
Array ( [id] => 6573420 [patent_doc_number] => 20020014703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Semiconductor flip-chip package and method for the fabrication thereof' [patent_app_type] => new [patent_app_number] => 09/935432 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9919 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014703.pdf [firstpage_image] =>[orig_patent_app_number] => 09935432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935432
Semiconductor flip-chip package and method for the fabrication thereof Aug 19, 2001 Abandoned
Array ( [id] => 664128 [patent_doc_number] => 07102216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making' [patent_app_type] => utility [patent_app_number] => 09/932290 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 6293 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102216.pdf [firstpage_image] =>[orig_patent_app_number] => 09932290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932290
Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making Aug 16, 2001 Issued
Array ( [id] => 6081028 [patent_doc_number] => 20020081780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Methods and apparatus for making integrated circuit package including opening exposing portion of the IC' [patent_app_type] => new [patent_app_number] => 09/931587 [patent_app_country] => US [patent_app_date] => 2001-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5558 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081780.pdf [firstpage_image] =>[orig_patent_app_number] => 09931587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931587
Methods and apparatus for making integrated circuit package including opening exposing portion of the IC Aug 15, 2001 Issued
Array ( [id] => 6716054 [patent_doc_number] => 20030027402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Method for reducing stress of sidewall oxide layer of shallow trench isolation' [patent_app_type] => new [patent_app_number] => 09/920011 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1537 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20030027402.pdf [firstpage_image] =>[orig_patent_app_number] => 09920011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920011
Method for reducing stress of sidewall oxide layer of shallow trench isolation Aug 1, 2001 Issued
Array ( [id] => 6897464 [patent_doc_number] => 20010045629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Leads under chip in conventional IC package' [patent_app_type] => new [patent_app_number] => 09/918739 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4515 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20010045629.pdf [firstpage_image] =>[orig_patent_app_number] => 09918739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918739
Methods for leads under chip in conventional IC package Jul 30, 2001 Issued
Array ( [id] => 1580991 [patent_doc_number] => 06423575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Hydrogen gettering structure including silver-doped palladium layer to increase hydrogen gettering of module component and semiconductor device module having such structure, and methods of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/917318 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4429 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423575.pdf [firstpage_image] =>[orig_patent_app_number] => 09917318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917318
Hydrogen gettering structure including silver-doped palladium layer to increase hydrogen gettering of module component and semiconductor device module having such structure, and methods of fabrication Jul 26, 2001 Issued
Array ( [id] => 1310269 [patent_doc_number] => 06617687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method of forming a test insert for interfacing a device containing contact bumps with a test substrate' [patent_app_type] => B2 [patent_app_number] => 09/916621 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6509 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617687.pdf [firstpage_image] =>[orig_patent_app_number] => 09916621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916621
Method of forming a test insert for interfacing a device containing contact bumps with a test substrate Jul 26, 2001 Issued
Array ( [id] => 1477954 [patent_doc_number] => 06451626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Three-dimensional stacked semiconductor package' [patent_app_type] => B1 [patent_app_number] => 09/917358 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 9770 [patent_no_of_claims] => 90 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451626.pdf [firstpage_image] =>[orig_patent_app_number] => 09917358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917358
Three-dimensional stacked semiconductor package Jul 26, 2001 Issued
Array ( [id] => 1086548 [patent_doc_number] => 06831361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Flip chip technique for chip assembly' [patent_app_type] => B2 [patent_app_number] => 09/911116 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3004 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831361.pdf [firstpage_image] =>[orig_patent_app_number] => 09911116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911116
Flip chip technique for chip assembly Jul 22, 2001 Issued
Array ( [id] => 6123556 [patent_doc_number] => 20020074642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Semiconductor device and package for containing semiconductor element' [patent_app_type] => new [patent_app_number] => 09/909597 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2763 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074642.pdf [firstpage_image] =>[orig_patent_app_number] => 09909597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909597
Semiconductor device and package for containing semiconductor element Jul 19, 2001 Issued
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