David E. Graybill

Array ( [id] => 774846 [patent_doc_number] => 07002236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Semiconductor package and method for producing the same' [patent_app_type] => utility [patent_app_number] => 09/898068 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4143 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002236.pdf [firstpage_image] =>[orig_patent_app_number] => 09898068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1191760 [patent_doc_number] => 06730134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Interposer assembly' [patent_app_type] => B2 [patent_app_number] => 09/897332 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3994 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730134.pdf [firstpage_image] =>[orig_patent_app_number] => 09897332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6755848 [patent_doc_number] => 20030003625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Leadframe pedestals for uniform die attach' [patent_app_type] => new [patent_app_number] => 09/896452 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3537 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003625.pdf [firstpage_image] =>[orig_patent_app_number] => 09896452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7465190 [patent_doc_number] => 20040053447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Leadframe having fine pitch bond fingers formed using laser cutting method' [patent_app_type] => new [patent_app_number] => 09/895501 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3611 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053447.pdf [firstpage_image] =>[orig_patent_app_number] => 09895501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7647043 [patent_doc_number] => 06476475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Stacked SRAM die package' [patent_app_type] => B1 [patent_app_number] => 09/892779 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476475.pdf [firstpage_image] =>[orig_patent_app_number] => 09892779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6269625 [patent_doc_number] => 20020105061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/892539 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6608 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105061.pdf [firstpage_image] =>[orig_patent_app_number] => 09892539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6753474 [patent_doc_number] => 20030001250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'TCP optical device' [patent_app_type] => new [patent_app_number] => 09/888379 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2544 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001250.pdf [firstpage_image] =>[orig_patent_app_number] => 09888379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1547562 [patent_doc_number] => 06445066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Splitting and assigning power planes' [patent_app_type] => B1 [patent_app_number] => 09/885491 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3090 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445066.pdf [firstpage_image] =>[orig_patent_app_number] => 09885491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7643587 [patent_doc_number] => 06429454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Semiconductor device with test circuit' [patent_app_type] => B2 [patent_app_number] => 09/877788 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3667 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429454.pdf [firstpage_image] =>[orig_patent_app_number] => 09877788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6028833 [patent_doc_number] => 20020017709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Assembly jig and manufacturing method of multilayer semiconductor device' [patent_app_type] => new [patent_app_number] => 09/876290 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5629 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017709.pdf [firstpage_image] =>[orig_patent_app_number] => 09876290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 620025 [patent_doc_number] => 07141448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials' [patent_app_type] => utility [patent_app_number] => 09/874666 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1713 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141448.pdf [firstpage_image] =>[orig_patent_app_number] => 09874666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6895222 [patent_doc_number] => 20010026012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method and apparatus for mounting component' [patent_app_type] => new [patent_app_number] => 09/873347 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9967 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026012.pdf [firstpage_image] =>[orig_patent_app_number] => 09873347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1225143 [patent_doc_number] => 06700177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Compact, surface-mounting-type, electronic-circuit unit' [patent_app_type] => B2 [patent_app_number] => 09/867919 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6149 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700177.pdf [firstpage_image] =>[orig_patent_app_number] => 09867919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 975970 [patent_doc_number] => 06933587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Electronic circuit unit suitable for miniaturization' [patent_app_type] => utility [patent_app_number] => 09/870129 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6580 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933587.pdf [firstpage_image] =>[orig_patent_app_number] => 09870129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6901498 [patent_doc_number] => 20010023081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Process of top-surface-metallurgy plate-up bonding and rewiring for multilayer devices' [patent_app_type] => new [patent_app_number] => 09/867364 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3887 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023081.pdf [firstpage_image] =>[orig_patent_app_number] => 09867364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1559674 [patent_doc_number] => 06436754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Selective salicide process by reformation of silicon nitride sidewall spacers' [patent_app_type] => B1 [patent_app_number] => 09/863221 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2216 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436754.pdf [firstpage_image] =>[orig_patent_app_number] => 09863221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6985601 [patent_doc_number] => 20010035571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Lead frame assemblies with voltage reference plane and IC packages including same' [patent_app_type] => new [patent_app_number] => 09/864698 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4634 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20010035571.pdf [firstpage_image] =>[orig_patent_app_number] => 09864698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1380388 [patent_doc_number] => 06544301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and apparatus for manufacturing solid electrolytic capacitor' [patent_app_type] => B2 [patent_app_number] => 09/861958 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 14342 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544301.pdf [firstpage_image] =>[orig_patent_app_number] => 09861958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6434391 [patent_doc_number] => 20020127772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Bumpless flip chip assembly with solder via' [patent_app_type] => new [patent_app_number] => 09/852824 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2648 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127772.pdf [firstpage_image] =>[orig_patent_app_number] => 09852824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6044422 [patent_doc_number] => 20020167077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Flip-chip package with underfill having low density filler' [patent_app_type] => new [patent_app_number] => 09/850922 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5360 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167077.pdf [firstpage_image] =>[orig_patent_app_number] => 09850922 [rel_patent_id] =>[rel_patent_doc_number] =>)